This paper assesses how modern tools can be used to address poweraware SI challenges associated with I/O modeling, interconnect modeling, simulation, and analysis. One of the toughest challenges in designing memory interfaces is accurately measuring timing while also considering fluctuations in power and ground rails due to simultaneously switching signals. Signal integrity (SI) engineers are increasingly insisting on “power-aware” SI analysis, where the effects of signal and non-ideal power/ground are considered when analyzing highspeed memory interfaces.
Addressing the “Power-Aware” Challenges of Memory Interface Designs
Cadence
