After months of waiting, we have seen Samsung Electronics’ applied extreme ultraviolet (EUV) lithography technology for D1z DRAM in mass production. Early last year, Samsung Electronics announced the world’s first development of both ArF-i based D1z DRAM and separately its EUV lithography (EUVL) applied D1z DRAM. TechInsights is excited that we have finally found Samsung’s and advanced D1z DRAM devices and confirmed details of this technology.

Samsung Electronics has developed its D1z 8Gb DDR4, D1z 12Gb LPDDR5, and 16Gb LPDDR5 DRAM devices as well with higher performance. We found both of the latter two devices (the D1z 12Gb and D1z 16Gb LPDDR5 chips) in the Samsung Galaxy S21 5G series; S21 5G, S21+ 5G and S21 Ultra 5G just released in January 2021.

12 Gb LPDDR5 chips are being used for Samsung Galaxy S21 Ultra 5G SM-G998B/DS 12GB RAM, while 16Gb LPDDR5 chips can be found in S21 5G and S21+ 5G 8GB RAM components.

When it comes to the D1z technology node, Samsung’s D1z 12Gb LPDDR5 DRAM generation has more than 15-percent higher manufacturing productivity compared to the previous D1y 12 Gb version. The design rule (D/R) is decreased from the 17.1 nm (in the prior D1y generation) down to 15.7 nm (D1z). The die size is also reduced, from 53.53 mm²(D1y) to 43.98 mm² (D1z); the die of the chip is about 18% scaled down from the previous version (Table 1).

A comparison of Samsung D1y and D1z LPDDR5 Chips with 8Gb, 12Gb and 16Gb.

Samsung Electronics used its most advanced D1z technology together with EUV lithography on 12 GB die with K4L2E165YC die markings, while D1z 16 GB LPDDR5 DRAM chips with K4L6E165YB die markings show non-EUV lithography die. It is likely Samsung initially developed D1z LPDDR5 products both with ArF-i based and EUV-based storage node landing pad / bit line pad (SNLP/ BLP) lithography, and now it produces all D1z LPDDR5 products with EUV SNLP/BLP lithography.

It applied HVM (high volume manufacturing) product in the DRAM industry and worldwide market, although Samsung released 1M sample modules with D1x EUV lithography applied in late 2019. Samsung D1z chips are likely fabbed from the second production line in Pyeongtaek, Korea.

Samsung DRAM cell design, a comparison of BLP patterns on D1z (a) without EUVL and (b) with EUVL.

For DRAM process integration for D1z 12 Gb LPDDR5 devices, Samsung adopted EUV lithography technology limited to only one mask, a Storage Node Landing Pad (SNLP on cell array)/Bit Line Pad (BLP on S/A) which measures around 40 nm critical dimension (CD or pitch) and 13.5 nm BLP line width on S/A (sense amplifier circuitry) area. Figure 1 shows a comparison of S/A BLP patterns on Samsung’s (a) D1z 16 GB LPDDR5 die with ArF-i based lithography and (b) D1z 12 Gb LPDDR5 die with EUV lithography. By using EUV lithography, BLP line edge roughness (LER) on S/A area is improved and bridge/short defects might be reduced.

Compared to Micron Technology’s competing D1z cell design, Samsung further reduced cell size (Samsung is at 0.00197 µm² versus Micron at 0.00204 µm²) and D/R (Samsung 15.7 nm vs. Micron 15.9 nm). Micron used ArF-i based lithography for all the photomask steps on D1z products, and it will not adopt EUV lithography for a while, including D1α and D1β. (Table 2)

Samsung DRAM cell size and D/R trends are shown in Figure 2 and Figure 3, respectively, including D3x through D1z. DRAM cell size and D/R scaling are getting harder and harder recently, however Samsung reduced D/R to 15.7 nm for D1z, which is 8.2 % scaling down from D1y.

Samsung will continue to increase EUVL steps for the next DRAM generation such as D1a (in 2021) and D1b (in 2022).