Anritsu Company will showcase solutions, technologies, and methodologies to accurately and efficiently verify high-speed communications designs during DesignCon 2023, January 31 – February 2, 2023 in Santa Clara, CA. Chip, board, and systems design engineers can learn of innovative testing approaches through demonstrations featuring vector network analyzers (VNAs) and bit error rate testers (BERTs); technical sessions, and panel discussions during one of the industry’s leading electronic design conferences.  

Innovative Test Solutions 

Related Resources

First Automated Test Solution for High-Speed Ethernet Cable
Langer EMV-Technik To Show HR-E 40-1 Near-Field Probe And PA 2522 Preamplifier At DesignCon
Keysight Introduces Optimized In-Line High Density In-Circuit Test System for Printed Circuit Board Assemblies
Anritsu Company

At DesignCon 2023, Anritsu will conduct product demonstrations on advanced testing approaches that address complex designs. Two test solutions to be shown in meeting room MR1462 are: 

PCIe® 6.0 Rx Compliance Test – Anritsu will demonstrate a single-instrument PCIe solution featuring its Signal Quality Analyzer-R MP1900A. The first solution to support the new PCIe 6.0 Base Spec. receiver test, the MP1900A assures the signal integrity of chip designs utilizing PCI 6.0. As shown in the demonstration, the all-in-one MP1900A simplifies the compliance test worst-case configuration while supporting accurate Rx Link Equalization (LEQ) evaluation.  

Signal Integrity – To characterize high-speed interconnects, printed circuit boards (PCBs), backplanes, fixtures, packages, and probes up to 70 GHz, Anritsu will show its  VectorStar™ 4-port broadband VNA. VectorStar can conduct accurate and repeatable single-ended, balanced differential, and mixed-mode S-Parameter measurements. Its ability to profile impedance along a line using Time Domain Reflectometry (TDR) and to simulate the eye diagram for a high-speed channel will be featured. Network extraction for fixture de-embedding and electrical-to-optical (E/O) and optical-to-electrical (O/E) transfer function measurements will also be shown. 

Technical Education 

Hiroshi Goto, Sr. Architect at Anritsu, will participate in two technical sessions and a panel discussion on emerging high-speed technologies: 

PCIe 6.0 Rx Test Requirements – On Thursday, February 2, Goto will give an overview on current requirements for PCIe 6.0 Rx calibration and testing. He will cover LEQ testing, as well as PAM4 Bit Error Rate (BER), Symbol Error Rate (SER), and jitter tolerance testing. Forward Error Correction (FEC) and Flow Control Unit (FLIT) mode uncorrectable burst error analysis will also be covered. 

USB4® Version 2.0 Tx and Rx Electrical Compliance – This February 2 technical session will provide an update on USB4 Version 2.0 electrical validation and compliance testing, associated test tools, and challenges in meeting USB-IF test program timelines. New USB4 Version 2.0 CTS requirements, PAM3 analysis for validation and debug, automated SigTest compliance testing, and receiver calibration and testing will be discussed.  

FEC and Signal Integrity – Goto will sit on a technical panel entitled The Case of the Closing Eyes: Bridging FEC to Signal Integrity on Tuesday, January 31. He will participate in a group discussion on FEC and how it can be impacted by signal integrity challenges, as well as testing architectures to help bridge FEC and signal integrity.  

Partnership Solutions 

Anritsu will participate in three joint demonstrations with fellow industry leaders. Each will highlight integrated solutions that address specific high-speed signal integrity challenges.  

Tektronix and Synopsys® – In booth #727, Anritsu will participate in a PCIe 6.0 live demonstration with Tektronix, Inc. and Synopsys that will highlight automating PCIe 6.0 Base Tx/Rx testing at 64 GT/s. The demonstration will feature the Anritsu MP1900A BERT with the Tektronix DPO70000SX real-time oscilloscope and silicon-proven Synopsys PCI Express 6.0 IP DUT.  

SENKO – The two companies will demonstrate 100 Gbps (53 Gbaud) BER test and PAM4 eye pattern analysis through low-loss, SN-MT connectivity from SENKO and the Anritsu BERTWave™ MP2110A and Network Master™ Pro MT1040A.   

Granite River Labs (GRL) – Anritsu and GRL will show an automated solution for high-speed serial bus receiver tests, such as PCIe, USB, Thunderbolt, and DP. It will feature the MP1900A with GRL software to establish a fast and flexible test method.