Today’s 3.3 kW switched-mode power supplies (SMPS) can achieve power densities of 100 W/inch³ by utilizing the latest technologies, including superjunction (SJ silicon) and SiC power MOSFETs in the totem-pole PFC stage as well as GaN power switches for high-voltage DC-DC stage operation. Digital control of the PFC and DC-DC stages is essential for maximum efficiency and robustness, as is the use of optimum gate drive solutions. To meet the latest design and application needs, Infineon Technologies AG introduces the next generation of the EiceDRIVER™ product family of dual-channel galvanically isolated gate driver ICs.

This product family spans multiple under-voltage lockout (UVLO) variants, isolation levels, and package options to provide a comprehensive solution for various applications. The new portfolio combines robust isolation technology that meets the latest isolation standards with excellent electrical parameters to deliver high efficiency and reliable operation over a wide temperature range, extending the design’s lifetime. These drivers can be used in a wide range of applications, including server and telecom SMPS, solar inverters and energy storage systems, motor drives and battery-powered applications, EV charging, and high-performance computing.

Compared to its predecessor, the new EiceDRIVER generation includes DSO 14-pin packages for extended channel-to-channel creepage and features dead-time and shoot-through protection, as well as a faster UVLO start-up time. It is also equipped with robust isolation technology that meets the latest isolation standards (VDE 0884-11, IEC 60747-17). In addition, it comes in highly compact LGA 4x4 mm² packages that allow for a space-saving of up to 36% in low-voltage applications. One of the most important improvements is the galvanic isolation integrated into the gate driver ICs, which is now certified according to IEC 60747-17. This certification ensures that these products are prepared for 20 years of operation and meet the highest safety standards.

The shortened UVLO start-up time (2 μs instead of 5 μs) enables a faster SMPS start-up and eliminates the risk of mains power-transformer saturation. In addition, the new ICs include a special output clamping circuit that implements an active output clamping approach to quickly clamp the output noise even if the channel is “inactive”. This is the most versatile approach to prevent dangerous half-bridge shoot-through events during boot-strapped start-up while the gate driver supply is still below the UVLO on threshold.

The new gate driver ICs feature configurable shoot-through protection and dead-time control built into their hardware. These second-level safety mechanisms provide additional protection to ensure safe and reliable operation. In addition, the innovative packaging design includes the removal of unused pins, formerly declared to be “no connects.” This feature enables higher channel-to-channel isolation ratings and provides higher PCB layout flexibility, making it easier for designers to develop their circuits.

Availability

The new dual-channel galvanically isolated gate driver ICs are available in leaded DSO and leadless LGA packages. DSO variants are offered in 14- and 16-pin configurations, both with 150 mil (“narrow body”) and 300 mil (“wide body”) form-factor. The LGA variants are offered in 5x5 mm² and 4x4 mm² dimensions.