March 21, 2017

Ensuring High Signal Quality in PCIe Gen3 Channels
By Anil Kumar Pandey

The challenge for PCIe, using high-speed 8-Gbps serial links, is it can suffer from a large array of physical phenomena. Addressing this challenge demands a PCIe interface simulation methodology.

Via Stubs – Are They all Bad?
By Bert Simonovich

We worry about via stubs in high-speed designs because they cause unwanted resonant frequency nulls which appear in the insertion loss plot (IL) of the channel. But are all via stubs bad?

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	Power-Aware Analysis Solution By Cadence Design Systems Inc.   This paper explains how a general power-aware SI solution not only should be capable of performing SSN simulations, but also capable of creating and extracting signal and power analysis-required models and running design checks with power-aware constraints.

Rohde & Schwarz Introduces Entry Level Oscilloscope

Rohde & Schwarz has broadened its growing oscilloscope portfolio with the R&S RTB2000, the first low cost oscilloscope to offer touchscreen operation as well as 10-bit vertical resolution.

Passive Plus Offers Extended Value Ranges for Traditional HI-Q/Low ESR Capacitors

Passive Plus, Inc. (PPI) now offers extended-values for the Traditional NP0, Hi-Q 0505 (.055” x .055”) -- now available up to 1,000pF and an increased operational temp up to 200°C.

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	EUT Monitoring with Digital Oscilloscopes By Rohde and Schwarz   This application note describes how to use the mask and limit test features of the R&S®RTO, R&S®RTE and R&S®RTM Digital Oscilloscopes for EUT monitoring of signal forms, jitter etc. with the R&S®EMC32 Measurement Software.

SI Journal Video Library

Videos from EDI CON USA, DesignCon and IEEE EMC events including demos, interviews and tutorial sessions.

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