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Debugging High-Speed SERDES Issues in Multi-board Interconnect Systems
By Dr. Syed Bokhari

An Outstanding Paper Award Winner at EDI CON USA 2017, this paper investigates SERDES performance in a multi-board system. The goal is to identify the cause of data transmission errors and variability between different differential pairs on the same board and between several boards.

Samtec Introduces New VITA 57.4-compliant FMC+ Loopback Cards

Samtec announces the release of the two new VITA 57.4-compliant FMC+ Loopback Cards. These new solutions provide FPGA designers easy to use loopback options for testing low-speed and high-speed multi-gigabit transceivers on any FPGA development board or FPGA carrier card.

Polar enhances Speedstack Si with fully integrated insertion loss field solver

Polar Instruments, announces a major enhancement for Speedstack Si at Productronica. Speedstack Si 2018 edition now contains an integrated insertion loss field solver which lets the user both design and add comprehensive insertion loss graphs and stackup specification into the report engine.
 

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How DDR Interfaces Can Be Accurately Analyzed Pain-Free

By Cadence
Learn how to use the Sigrity Finite Difference Time Domain (FDTD) simulator to accurately predict the impact of simultaneous switching noise (SSN) in a system context.

New Classified Ads Job Posting Area

Post job openings for free in our new classified job listings or peruse the listings for career opportunities:

Digital Circuit Analysis Engineer (Los Angeles/Denver)
AEi Systems is looking for highly-skilled electrical engineers who are experts in Digital Signal/Power Integrity Analysis. Career Level Required: Experienced Analysts, Design Engineers and Digital Troubleshooters (Non-Manager). Learn more.

Upcoming Webinars

The 3 Necessary Evils - Discover and Solve PI, SI and EMI Issues Affecting Designs

Today a lot of electronic designs are faced with multiple challenges while integrating digital, analog and RF circuits. To achieve compliance and relevant performance, designers need to characterize power lines and tracks, high speed comms and verify their integrity while not causing any bigger EMI issues. Learn about the relevance of power integrity, signal integrity, and EMC.

In-Situ De-embedding

Traditional de-embedding methods can give non-causal errors in device-under-test (DUT) results if the test fixture and calibration structure have different impedances. This presentation introduces In-Situ De-embedding (ISD) to address such impedance differences using software instead of hardware, thereby improving de-embedding accuracy while reducing hardware costs.

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