Articles by Bert Simonovich

This DesignCon 2024 paper, a Best Paper Award winner, introduces a new process utilizing heuristics to determine laminate anisotropy based on Dk/Df construction tables provided by laminate suppliers.

In this guide to paper submission best practices, Bert Simonovich reviews DesignCon's CFA evaluation criteria and requirements, offering helpful advice for first-time submissions.

Since woven glass PCB substrates are anisotropic, EDA design and modeling software hoping to advance AI and ML algorithms should have provisions to model anisotropic material, especially via transitions. In this article, Bert Simonovich discusses the importance of having an awareness of the test method used by CCL suppliers for accurate modeling and simulation. Simonovich covers how the use of out-of-plane Dk_z values instead of in-plane Dk_xy values for via modeling can cause misleading simulation results, which may result in reduced margins and potential compliance test failures when the design is built and tested. 

In this article, Bert Simonovich explores how to avoid “garbage in, garbage out” with field solvers by building an understanding of the nuances of PCB fabrication processes, the interpretation manufacturers’ data sheets, and the tool’s user interface.

In this article, Bert Simonovich discusses crosstalk, NEXT vs coupled length in stripline, NEXT vs coupled length in microstrip & FEXT. Read on. 

In part one of this article, Bert Simonovich explained how air entrapment is the primary reason for Dkeff and phase delay discrepancies between simulation and DUT measurements. Read on to discover how to fix this issue.

Fiber weave effect (FWE) skew, also known as glass weave skew (GWS), is becoming more of an issue as bit rates continue to soar upwards. Today’s 56 GB/s is state of the art in high-speed routers and 112 GB/s is just around the corner. While next-generation PCIe, used in the personal computer and server industry, is rapidly moving to 64 GT/s. 

In this article, Bert Simonovich shows how using Dkeff calculated from phase or time delay measurement method will lead to inaccurate simulation results for printed circuit board (PCB) transmission lines.

Designing the right PCB stackup can make or break product performance. If the product has circuitry that is impedance and transmission loss sensitive, then paying attention to conductor surface roughness is paramount. Sometimes, however, the roughness of adjacent reference plane(s) is overlooked. If the adjacent high-speed signal layer uses smoother copper than one or both reference planes, a higher insertion loss than expected for that layer will occur and possibly cause a product to fail compliance. So, how is this determined before finalizing the stackup? Read on to find out.