eSilicon was in the Samtec booth at DesignCon 2019 presenting their collaboration with Wild River Technology to develop an advanced test system that addresses the difficult signal integrity demands of 56/112G PAM4 operation. The test system design utilizes the upcoming IEEE P370 standard in association with compliance metrics 802.3bs, OIF CEI – 56G PAM4, and COBO to validate the required performance.

The IEEE P370 standard addresses the quality of measured S-parameters for PCBs and related interconnects at frequencies up to 50 GHz. This might include (but is not limited to): test fixturing, methods, and processes for controlling the accuracy and consistency of measured data for broadband signals with frequency content up to 50 GHz.

Keysight’s Advanced Design System was used to explore the power spectral density examining how much bandwidth is needed for effective testing and what specific metrics of IEEE P370 are most important. These metrics include parameters such as return loss, equivalent return loss, time-domain reflectometry (TDR) and impedance analysis. eSilicon’s 56G PAM4 and NRZ DSP-based 7 nm SerDes was used to drive the communication channels. The design employed a channel-modeling platform to improve de-embedding quality past 70 GHz, establishing clear targets of equalization and creating an advanced reference design suited for immediate 3D electromagnetic design.

The core of the design was Samtec’s Bulls Eye® Test Point System. Three independent teams worked on the design in order to create some competition to drive the optimal solution. Two teams were resident at Wild River Technology and used the ANSYS® HFSS™ and Simbeor THz software, respectively. A third team was resident at Samtec where ANSYS® HFSS™ was utilized. The teams worked in parallel but worked independently, creating competition to see which could develop the most optimal solution. Then they all shared their final results which were fairly consistent validating that fact that the implementation was sound. The process took 6 weeks to create a reference design with first pass success. The BER greatly exceeded the goal of 1E-4 achieving 1E-11. High-volume sockets are the next thing the group plans to attack.

From their press release: Al Neves, founder and CTO at Wild River Technology, said “Our design approach reduced spins and shortened schedules, allowing us to achieve conformance to the emerging IEEE P370 standard through a systematic design methodology. I got the idea for this approach from the early Apollo missions where they calculated launch trajectories with three teams working independently and concurrently. We all know this resulted in success for the Apollo program and it has resulted in success for our test system design as well.” Al also described the teams as a synergistic blend of individuals that made cohesive teams.

“We are delighted with this test system design — our next phase is to design and build a test socket suited for 70 GHz,” said David Axelrad, senior director of IP marketing at eSilicon.  “There are only a few companies that have silicon working at these speeds, and eSilicon is focused on being the first in production with a true long-reach DSP SerDes in 7 nm.”

This was a true collaboration between many companies and shows how open sharing of information leads to successful first pass development cycles. Many companies are hesitant to be this open and share data but the learning that engineers attain through such a process is invaluable.