I was onsite at DesignCon last week for the Signal Integrity Journal and saw many old friends and familiar faces. My hearty congratulations go out to this year’s Engineer of the Year, Heidi Barnes, who was also a short-course presenter at the first EDI CON USA  and someone for whom I have a great deal of respect. After her win, Heidi was also part of a panel of other Engineer of the Year winners, including Eric Bogatin (our Signal Integrity Journal editor) and Mike Steinberger, the 2015 winner.

During the panel (image right), Heidi, Eric, and Mike talked about what’s next for SI and PI engineers, focusing on the importance of new materials, bringing together simulation and measurement (especially for power integrity), and watching out for higher cross talk and channel interactions at higher data rates.  Eric suggested that embedded instrumentation could be key to future successes. For new engineers, they recommended trying to have a broad experience as well as trying many different things.            

On the show floor, I ran into Al Neves (an SI Journal Editorial Advisory Board member, image left). Also on the show floor, I stopped by the Museum of Interesting Things, which featured some frighteningly recent items that are already obsolete! The museum is run by Denny Daniel, and was fun to visit (image below). For a run down of the exhibit hall, see “Hanging out with Chiphead.”  For an image gallery of the event, see DesignCon 2017 Picture Gallery.

So, now that you’ve had your opportunity to speak at DesignCon, I invite you to submit an abstract for EDI CON USA, which will take place in Boston, MA September 11-13. This will be the second year for EDI CON in the US (its 5^th year in China).  The EDI CON technical program is made up of two pillars, the SI/PI/EMC/EMI pillar, and the RF/Microwave pillar. This year, our high-speed digital conference chair is Istvan Novak of Oracle and our RF/microwave chair is Tom Cameron of ADI. The call for abstracts is open now, and submissions will be peer reviewed by our EDI CON USA Technical Advisory Committee.

In addition to the Signal Integrity, Power Integrity, and EMC/EMI tracks, the EDI CON USA conference also has a Simulation & Modeling track as well as a Test & Measurement Track. Having both high-speed and high-frequency engineers in one place provides a great opportunity to share innovations and get insights on common challenges. I hope you consider sharing your work at this uniquely east coast venue. Here’s a list of some sample topics in the high-speed tracks:

Signal Integrity sample topics:

• Channel optimization for low jitter and BER
• Common signal integrity
• Signal integrity benchmarking
• IBIS/AMI model verification
• PAM4 channel optimization
• Test fixture characterization and de-embedding
• Chip/package/PCB co-design
• Pin-assignment optimization
• High-speed connector characterizations and applications
• High speed memory design
• SerDes design flows
• HD signal routing
• New materials for high-speed designs
• Channel Metrics: single bit response, S-parameters, eye diagrams and contours, COM, and BER

Power Integrity sample topics:

• Designing power interconnects
• Power distribution and management
• Power distribution network design methodologies
• Supply noise modeling and analysis
• Core logic voltage noise
• On-die capacitance
• Die package resonance
• Decoupling capacitor integration
• Power distribution network impedance
• Coupling among power domains
• Power filters
• Measuring very low power signals
• Design and characterization of power sources, DC-DC converters

EMI & EMC sample topics:

• Modeling for product compliance
• Mitigating EMI issues
• Conducted emissions
• Antenna and probe design
• Near field/far field effects and measurements
• Common mode chokes

Abstracts for EDI CON USA are being accepted now through April 3. The Technical Advisory Committee reviews all abstracts. All submitted and accepted papers are considered for the EDI CON USA Outstanding Paper Awards.