As expert as I am in signal integrity and power integrity, I always learn something new and valuable when I listen to experts. Here are four presentations from which you will gain insights into PDN design for PCBs. 

In October 2024, Balaji Sankarshanan, from GE Health Care, organized the fourth annual IEEE Midwest PCB Fest. He convinced three industry experts, alongside myself, to present on any topic they chose related to PDN design and the PCB.  All of these presentations were recorded and are available online for free viewing. These are four exceptional presentations on the theme of PDN design and PCBs, all in one place.  are the highlights from these four presentations. 

The Role of Decoupling Capacitor Optimization in PCB Power Delivery

With Heidi Barnes, Keysight. Watch here.

In PDN design, the target impedance figure of merit is the most important design goal. Generally, it should be below 10% of the device load impedance to keep the PDN voltage drop to an acceptable level. 

In AI processors, the power consumption is over 1000 W. This means with 1 V power rails, the target impedance must be in the µΩ range. Engineering the impedance of the PDN to keep it below this level requires careful attention to board-level inductance. This means leveraging EM simulation tools. In the µΩ range, every uH is important.

It is not always true that the more capacitors, the better. An example of the importance of careful simulation is an FPGA board, where adding additional capacitors actually increases the impedance at high frequencies due to the introduction of additional parallel resonances. Optimized values, location, and numbers are what are important for the lowest impedance.  

Designing the PDN is about optimizing three different elements of the PDN: the VRM, the discrete capacitors, and the package and on-die capacitance. These elements of the PDN affect the impedance in three different frequency ranges, as shown in Figure 1.

Figure 1. Three frequency ranges where the three PDN elements dominate.

At each interface is a parallel resonance, defined by an inductor on the low-frequency side and a capacitor on the high-frequency side. If the peak is critically damped with some series resistance, like from the VRM, the ESR from the capacitors, and the on-die spreading resistance, it is the Sqrt(L/C) that determines the peak impedance. 

At the VRM and PCB interface, we need to optimize the bulk capacitor value to achieve a sufficiently low parallel peak impedance. At the PCB and package die interface, the Bandini Mounting peak impedance is reduced by minimizing the L as much as possible. 

We do this in all the usual ways: low mounting inductance, capacitors spread out around the package, multiple vias, and low spreading inductance in the PCB. All of these features require EM simulation of the PCB to calculate the loop inductance and the impact of design features on their loop inductance contribution. 

Elevate Your Power Integrity Measurements: Analyzing Large Signal Phenomena and Crosstalk in Time and Frequency Domains and Avoiding Ground Loop Effects

With Martin Stumpf, Rohde and Schwarz, and Ben Dannan, Signal Edge Solutions. Watch here.

PDN crosstalk is really about coupling between elements associated with the PDN. It can contribute to jitter and noise. It is very commonly found on FPGA board that can have as many as 24 different power domains. 

Measuring these effects are generally more complicated than simple impedance measurements. Here is an example of a test system, in Figure 2.

Figure 2. A typical test system to measure the crosstalk between power domains.

The power rail drives 100 A in one power domain and a 5 A load in another power domain. 

When the 100 A source was constant, there was no crosstalk on the 5 A supply. However, when the 100 A supply current was switched to 50 A, considerable crosstalk was observed on the 5 A supply, as indicated by the change in the spectrum of the voltage noise on the 5 A. This is shown in Figure 3.

Figure 3. The difference in the spectral noise on the 100 A and 5 A supplies when the 100 A supply changed its current draw.

In this measurement, the spectrum of the power rail voltage noise with constant current on the 100 A supply is in gray. There is little noise on the victim PDN. However, when the high current supply switches, the voltage noise spectrum on both rails, shown in pink, increases dramatically. This is a direct measure of the crosstalk between power domains, happening at the edges of the changing currents. 

One of the challenges when measuring these sorts of power rails is the ground loop created by the common earth ground and chassis ground connections from the source power supply, the on-board VRMs, the probe return paths and the scope input channel. 

This ground loop can be broken using a ground isolation probe adaptor, in this case, the PicoTest J2115A isolator. In some cases, the impact of the ground loop can be as much as 100 mV to 400 mV. If you care about accurate PDN noise and crosstalk, you must pay attention to the ground loop problem. 

When measuring large signal transients, when large currents, like a 160 A switch, there can be as much as 50 mV variation out of a few 100 mV of peak voltage of switching noise. This is due to the variation in dI/dt in each cycle. Careful attention to the measurement setup and probing can significantly impact the accuracy of multi-channel and high-current switching noise measurements. 

SI/PI Challenges in the Era of AI/Data Centers/HPC

With Steven Sandler, Picotest. Watch here.

In AI based data centers with more than 2000 A used by one device, the measurement challenges are just as important as the design challenges. In these applications, “Everyone is learning at the same time.”

Steve described five revolutions in electronics technology, especially in power electronics: 

• Introduction of the vacuum tube in 1904
• Introduction of the BJT in 1947
• Introduction of the MOSFET by Alex Lidow in 1979
• Introduction of GaN by Alex Lidow in 2009
• Introduction of AI in early 2020’s

In the current AI data center application space, the currents are much higher, the dI/dt are much larger, and the target impedances are much lower. We will need advances in capacitors, in EM tools, in circuit simulation tools, in PCB board layout for lower IR drops to meet these challenges.

It is important to keep in mind that while the impedance of the PDN interconnects may be linear, the output impedance of the VRM is not. As a system, it is not time invariant or passive. This means we need to analyze the VRM in terms of the small signal response and the large signal response using a nonlinear model.

At 150 A, many connectors melt. One way to reduce the current is to increase the source voltage. A typical standard is 54 V. The first stage voltage regulator reduces this down to 13.5 V. This is a 4:1 step-down buck regulator. 

Another trend is vertical power delivery. This means placing the VRM under the BGA footprint with vias directly up to the BGA power and ground balls.

Measuring low impedance structures is a challenge. As Steve suggests, initially, you always want to measure something for which you know the answer. But, how do you even make a component that has 10 µΩ of impedance? He partnered with Keithley to create very low resistance standards, which anyone can use to verify their measurement system, as shown in Figure 4.

Figure 4. Examples of very low resistance standard, which can be used to verify the performance of low impedance measurement systems. 

One way of measuring ultra-low impedance with large currents and not consuming a lot of power is by doing the measurement in a very short period of time. Using the step response or pulsed sine waves, the whole impedance profile can be measured in a few milliseconds. 

“Power supplies don’t earn any money. It’s the signals that do.” However, they are becoming increasingly important as limiting factors in next-generation AI-driven products. 

PCB Applications of a $300 VNA to 4 GHz

With Eric Bogatin, CU Boulder. Watch here.

Can you really do anything useful with a $300 VNA? The answer is yes. I show two examples of important measurements. The first is measuring the Dk dispersion curve of a PCB laminate using the delta L method, and the second is measuring the RLC properties of a capacitor with an impedance in the mΩ range. 

Figure 5 shows the TDR response from the 4 GHz VNA for these two length traces.

Figure 5. The test board for the delta L method and the measured TDR response of the two traces.

From the S21 phase, the time delays of the long and short lines can be extracted. The difference is the time delay of the difference in length, independent of the launches. From this, the Dk over frequency can be calculated. In this board, we measured a bulk Dk of 4.84. The vendor had told us it was 4.6.

The second example is measuring low impedance decoupling capacitors using a 2-port VNA. This uses a simple test board, soon to be open-sourced, which allows the 2-port measurement of various capacitors. An example is shown in Figure 6 below. This shows an ESR of 2.5 mΩ for one of the capacitors, about at the noise floor of the VNA.

Figure 6. Test board and the measured impedance profile of 1206 capacitors. 

A few other examples are shown to illustrate how the mounting capacitance of the capacitor influences its loop inductance. Additionally, the difference in impedance between a leaded capacitor and an SMT capacitor is illustrated.

If you have a few hours of time to invest in learning about PDN principles, these recordings will be well worth your time.