In this article, we will demonstrate some examples of on-die power rail measurements. 

For this project, we will use an Atmel 328 microcontroller demo board, prepared with firmware to control it explicitly for our purposes, and with coaxial cables connected between the I/O pins and the input to the active probes of the scope. This interconnect provides a high bandwidth transmission line path for the signals.  Test equipment for these examples is the Teledyne LeCroy HDO8108A oscilloscope and three Teledyne LeCroy RP4030 active voltage-rail probes (See Figure 1).

Figure 1

Here’s the setup of our instrumented demo board: One I/O (pin 8) will be toggled as a trigger for the oscilloscope to give us a reference for subsequent operations. The trigger is  a single high-low pulse lasting one clock cycle. . So as not to load that line down with the 50-Ω input of the coax cable, we add a 450-Ω resistor in series with the coax cable where it is soldered to the board trace. Thus, it's going to give us 10X attenuation, but given that it's only triggering the oscilloscope, we don't care about SNR for this signal.

Some other pins will be loaded with either the 50-Ω or the 1-MΩ inputs to the oscilloscope so we can turn that DC load on and off and see the impact of extra I/O current on the die.

Another pin is our quiet-low pin set as a low output, which effectively connects it output to the Vss on the die and monitored with a voltage-rail probe. Meanwhile, another pin is a quiet-high pin, set as a high output, which effectively connects its output to the  Vcc on the die and similarly monitored. Both of these pins come off the board into a coaxial transmission line and straight into the rail probes.

We'll also monitor the 5-V line on the demo board itself. Several other pins are configured to drive LED loads that we can toggle on and off and see the impact of these loads on the rails.

Characterizing the On-Die Power Rails

For this example, the microcontroller's clock rate is 16 MHz (1 cycle = 63 ns). When the DUT is in the idle state, with no I/O switching, nothing should be happening on the die . In this state, we can look at the on-board power-distribution network's (PDN's) noise level as well as some noise emanating from a switch-mode power supply and a low-dropout regulator. We should se the lowest noise behavior.

Even without I/O switching, the microcontroller will be continuously running background maintenance functions like watch dog timer, other timing and counting, and running the clock.  With the I/O switching, we should see the ground bounce and power droop resulting in rail compression on the die.

Now that we're ready to begin some on-die power-rail measurements, it's a good idea to step back for a moment and anticipate what these measurements should show us. What actually happens on the die when CMOS gates are switching on and off? What should we expect to see on the on-die power rails? And what happens at the clock edges?

When the I/O gate switches from logic low to logic high, current from the power-distribution network (PDN) on the die will flow from the Vdd/Vcc rail all the way through to the Vss rail (Figure 2). This is because the capacitance of the output line is referenced to the capacitances of both rails when the device switches from low to high.

Figure 2

What happens when the I/O gate switches from high to low (Figure 3)? It's logical to think that it would simply discharge the capacitance across the N-channel gate and that current flow would be local to that loop. But on the die \ that output capacitance is also referenced to Vdd/Vcc through the on-die interconnect capacitance. When the output line switches from high to logic low, we discharge the charge in that capacitor through the N-channel gate, but we also have a voltage drop through the capacitance of the interconnect to Vdd.  The dV/dT to the Vdd rail drives current through this path as well.  

Figure 3

So even when the I/O switches from high to low, we will still have PDN current flowing through the PDN's impedance. That, in turn, means that we will see current flowing on both edges of the clock.

Gates will switch on both edges of the clock.. Generally speaking, depending on the logic design, when the clock edge rises, the gates are switched, and when the clock edge falls, the gates are latched. In latching, there should be less current draw than in switching. So even though we get PDN current flowing between Vdd/Vcc and Vss on both clock edges, there should be an asymmetry in that current flow (Figure 4).

Figure 4

That sums up our expectations of what we should see on the on-die power rails. With no I/O switching. Now let’s look at the actual measurement results.

Having reviewed the test setup for on-die power-rail testing and our expectations of what the tests should show us, let's walk through the measurements and look over the results. We'll also note whether our results align with our expectations..

First, let's look at the MCU's idle state and with only the low-current trigger I/O functionality in play (Figure 5). The top trace is the quiet-high line (Vcc on-die) while the bottom trace is the quiet-low line (Vss on-die), both relative to the ground on the demo board. This is a direct measurement of the voltage noise on the power-distribution network (PDN) on the die. In the idle state, there is no I/O switching. This PDN current flows through the package. Some of the noise is due to on-die PDN impedance and some due to package impedance. The clock edge noise due to on-die core logic switching is clearly evident with about 75 mV peak to peak noise.

Figure 5

The center yellow trace in Figure 5 is the single trigger pin we use as the reference for the scope. It is drawing a small amount of current; it's a 500-Ω load with a 5-V source, so it's drawing about 10 mA when it switches on.

We can use our built-in parameter extraction calculator to measure the important figures of merit for the trigger signals. The rise time is 3.2 ns, which give us the rise time of the output drivers in this particular Atmel MCU. Pulse width measures 64 ns; the clock frequency is 16 MHz, which makes this one clock cycle. The I/O switches high on the leading edge of the first clock cycle and switches low on leading edge of the second clock cycle.

Before and after the trigger event, the voltage noise in the idle state reflects other activities of the MCU such as looking for interrupts and the like.

Also, note that when the output switches from high to low, there's a collapse in the power rail and a recovery with some overshoot. That's the impact on the power rail of that small 10-mA switching current. The noise on the quiet line, looking at the on-die Vss rail, is the ground bounce when the I/O switches from high to low.

That's what's happening on the die. What about the printed-circuit board? Figure 6 shows us the board-level Vcc supply relative to ground. At top is a 5-V USB laptop port that's powering the MCU, and it displays the typical signature of a switch-mode power supply (SMPS). The power supply has a switching frequency of about 50 kHz. Noise is 30 mV pk-pk, which is less than 1% noise. At bottom is the low-dropout (LDO) regulator on the board, which is powered by an external 9-V DC supply. That supply is a typical SMPS. The LDO filters most of the switching noise out. The voltage noise here is a scant 2 mV pk-pk, and this is where the signal-to-noise ratio of our measurement system matters a lot.

Figure 6

Next, let's see what happens when we start other I/Os toggling on and off. Shown in Figure 7 is the voltage noise on the die (quiet-high line/Vcc at top in white), and one of the other I/Os switching (V_I/O at center in purple). As this I/O switches, we see more current flow in the quiet-low line/Vss (at bottom in blue) and some negative ground bounce. When the I/O switches on, a large amount of current flows through the ground return, which sees inductance on the package lead. Everything on the die that shares the Vss line sees this voltage noise.

Figure 7

On the on-die power rail itself (Vcc), we can see the clock noise in the left-hand portion of the trace before the I/O switches on. When the switching occurs, we can see a very large voltage drop, as well as more voltage noise. It's a drop of about 300 mV caused by several I/Os switching at once (only one of which is seen in the screen capture of Figure 7). When V_I/O switches from high to low, there's a voltage bounce in Vss of about 200 mV.

Meanwhile, on the board (Vcc-board at center in red), very little noise is observable, with a voltage drop of less than 30 mV. It's the transient currents happening on the die that are the aggressors in this scenario. The noise on the die has to pass through the inductance of the package leads and on-board capacitance. This is an LC low pass filter. No high frequency components make their way through this filter to the board level Vcc.

Lastly, let's look at the waveforms when a bunch of I/Os are switching. We'll use a longer on-time for the I/Os and have the time base zoomed out for a bigger picture (Figure 8). At top in green, we see the quiet-high/Vcc line on the die. With our vertical scale set at 200 mV/div, this is a voltage drop of almost 600 mV, from 5.1 V to 4.5 V. You can see a bit of a transient signature in the trace as well as evidence of a large low-frequency or DC component. This indicates that there's a good amount of IR drop in the on-die PDN.

Figure 8

Meanwhile, the voltage on the board (red trace) has much less voltage noise, a drop of just 12 mV and a quick 2-μs recovery. As we'd expect, we see a critically damped response. The SMPS voltage recovers because the sense line pulls the voltage back up, after the slight voltage drop from the on-die current transient. There's a huge difference between on-die voltage noise and on-board voltage noise. There's 250 mV of transient ground bounce noise in the package caused by a large current switching through the package inductance.

This example illustrates that just because we measure the voltage noise on the board, we really know very little about the noise on-die. If the aggressor of this on-board noise is on the board, the on-die noise will be less. If the aggressor of this on-board noise is on the die, the on-die noise can be much larger.

This is an important lesson to keep in mind when analyzing power rail noise in your applications.  Using the techniques illustrated in this note, you can sometimes get a direct measure of the noise on-die, which is where it really matters.

Previously published version in the Teledyne LeCroy Test Happens Blog.