EDI CON Online

Title: System Oriented Testing for Memory Interfaces  

Date: October 20, 2020

Time: 10:30am PT / 1:30pm ET

Sponsored by: Introspect Technology

Presented by: Erin Holley, Senior Member of Technical Staff

Abstract:
Next-generation data center and server architectures rely heavily on high-speed signaling interfaces. No longer restricted to the networking sub-systems of the data center, these high-speed interfaces are used to connect processors, AI hardware accelerators, switching and routing fabrics, and of course extremely high-density memory channels. Testing these highly parallel signaling interfaces represents a particular challenge due to the tight interaction between environmental parameters, physical layer effects, and protocol payloads. Memory test solutions in particular must be capable of adapting to protocol changes and in-depth compliance measurements, as well as providing a means to perform system-level functional validation. This workshop will include an overview and demo of Introspect’s highly parallel memory interface test solution, showing the role it plays in ensuring the proper characterization and screening of DIMMs and components for the DDR5, and similar, memory standards.

Presenter Bio:

Erin Holley is a Senior Member of Technical Staff at Introspect Technology, a leading manufacturer of innovative test and measurement products for high speed digital applications. A graduate of McGill University in Montreal, Canada, Erin currently leads the development of Introspect's memory interface test solutions, and she is responsible for delivering and sustaining highly-parallel test instruments that operate at data rates of up to 32 Gbps. Erin is a member of the JEDEC Association, the MIPI Alliance, and PCI-SIG, and she regularly represents Introspect Technology at industry events. Her main interests are in high-speed digital design and test system architecture. She works with vendors at all stages of DDR memory design, translating difficult industry challenges into extremely compelling design validation tools for engineers. 

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