Decoupling Capacitor Optimization for Power Integrity

March 29, 2018
10am PT / 1pm ET
Sponsored by Keysight Technologies
Presented by Heidi Barnes, Signal and Power Integrity Applications Engineer

Why this webcast is important:

Selecting the right decoupling capacitors for flat target impedance improves the power integrity of a power delivery network while often decreasing cost. Modern high speed designs have both mission mode simultaneous switching noise (SSN) and state change step loads that that exceed the response time of the voltage regulator module (VRM), and are lower frequency than what the on-die and package capacitors can handle. The decoupling capacitors must fill this gap and deliver the required power in this mid-range of frequencies between the VRM and the package/die target impedance bandwidth. The decoupling capacitors must also insure stability with the voltage regulator and minimize the “bandini mountain” parallel resonance with the package inductance.

Learn how to use ADS PIPro to generate Electromagnetic (EM) models that account for PCB parasitics and then use the models to optimize the decoupling capacitors for low milliohms of impedance. See an example solution with a full end-to-end circuit simulation using state-based-average models for the point of load (POL) dc to dc converters, PCB EM models, and package/die models.

Who should view this webcast:

Power integrity and signal integrity engineers responsible for the design and fabrication of high speed digital systems with printed circuit board power delivery networks. Managers that want to understand the new design space challenges faced by the Power Integrity engineer as voltages continue to drop and currents increase, and achieving less than 10mV of ripple noise is considered easy.