Items Tagged with 'VRM'

This paper addresses the challenge of how to simulate the power integrity ecosystem and include the feedback loop and switching noise of a switch mode power supply (SMPS) without waiting days for the simulation results. The solution presented here uses control loop theory state space equations to create a behavioral model of an SMPS that allows for fast simulation.

Benjamin Dannan and Steve Sandler teamed up to explore the tradeoffs for various calibration methods and offer some recommendations and considerations to make accurate sub-milliohm impedance measurements.

The voltage regulator module (VRM) contributes system level noise in several ways. Power integrity (PI) engineers tend to focus on transient voltage noise related to high-speed dynamic current. Many PI simulators ignore the VRM noise and use an ideal resistor and inductor model to represent the VRM. This overly simplistic approach misses many potential system level issues.

This paper reviews four levels of VRM models that VRM designers, board level interconnect designers, semiconductor designers, and product managers often use to explore design tradeoffs throughout the PDN system. The choice of which one to use involves considering engineers’ levels of expertise and what problems they expect to analyze. Some tradeoffs and relative merits of the models are described.

VRMs and VRM controllers are often selected based on size, efficiency, price, or a relationship with the manufacturer. This often leads to a poor VRM selection, requiring additional engineering resources, greater time to market, as well as, higher BOM costs to correct the deficiencies. In this article, we evaluate the choices, define some useful figures of merit, and provide specific selection suggestions.