Items Tagged with 'IBIS'

Past and present officers gather to celebrate IBIS – and cut the cake!

Since the inception of IBIS, the IBIS Committee has been working to improve and accommodate limitations of the model. This article gives a synopsis of that history, along with detailing the latest version, IBIS 7.1.  

Join Eric Bogatin, SIJ Technical Editor in his conversation with Donald Telian, the father of IBIS models, and learn about the value of Serdes equalizer settings.

One of the main challenges of performing analysis upstream is incomplete models used in analysis. Normally the full physical layouts from which extractions are performed on interconnect do not yet exist. So how does one fill in the blanks to perform early analysis?

Eagerly anticipated, the next generation of DRAM technologies (DDR5/LPDDR5) are presently being validated in the lab by leading silicon vendors worldwide. This latest generation has a big surprise in store for hardware engineers and SI specialists that need to simulate such systems. DDR5 will introduce decision feedback equalization (DFE) for the DRAM receiver for the very first time.

Read on for a history of Touchstone and find out how you can shape its next iteration.

There was a time when the signal integrity of connections between digital ICs could be nearly ensured by following one simple rule: don’t connect more than some maximum number of input pins to any single output pin. Often the fanout limit would be around 7. No models, no simulations. Everything we needed was in the thick books of vendor datasheets that filled our shelves, the tree-killing viral precursor to AOL installation CDs. Ah, those were the days!

Ken Willis provides some background on the IBIS AMI standard and looks ahead to what’s next.