Items Tagged with 'DDR4'

Providing the company's customers with higher-density options for a wide range of applications, the new devices are built on a new process technology to deliver improved performance—with lower power consumption and higher speeds and transfer rates—at a lower cost.

Teledyne e2v and Texas Instruments (TI) have collaborated on a new radiation-tolerant DDR4 modular platform to help satellite OEMs streamline their system development work.

In earlier DDR systems, the clock, command, and address signals (here in referred to as C/A) were distributed to multiple DRAMs using a forked topology, in which these signals propagate to all the DRAMs in the system at approximately the same time. The propagation delays on the command and address lines (in such systems) introduced timing skew into the system, limiting the operating frequency of the bus and eventually impacting the performance of these memory systems.

Teledyne e2v semiconductors’ ultra-high density DDR4 memories continues, now that flight models are being shipped to key customers around the world and is now moving into the mass production phase, with the space-grade radiation tolerant DDR4s being available.
 

As DDR data transmission rates continue to increase, the signal integrity of the DDR channel has become one of the most critical concerns. This article takes an extensive look at the impact of via stubs on the impedance of the signal lines on DDR4 memory, including test cases and ways to optimize design.

The goal of power integrity (PI) analysis is to ensure not only sufficient but also stable power to all chips in a system. This article uses the example of a DDR4 application to explain the choices surrounding the use of decoupling capacitors to reduce impedance, and which performance parameters are critical to success.