Which Discontinuities are Small Enough to Ignore?

A 60 mil via is too small to worry about, right? And that 20 mil solder pad – the signal certainly won’t “see” that, correct?

If you work with high-speed signals, no doubt you’ve asked these questions and someone told you “It depends.” You might have your own rule-of-thumb (RoT) that helps you decide which discontinuities – or “features” – might impact signal quality. In this article, I share my favorite rule-of-thumb related to feature size and demonstrate its use. Read on for an explanation of what you need to pay attention to when, and why. And yes, “small” changes with frequency.

Size, Frequency and High-Speed

When edge rates were 10 nanoseconds, we had the luxury of simply connecting signals without thinking about high-speed effects. In fact, after three dozen years of puzzling over interconnects, my favorite definition of “high-speed” [1] is still: “A net can be considered ‘high-speed’ when you have to do something other than simply connect it.” In other words, something beyond connectivity is required to make the signal work, such as length, impedance, termination, timing, equalization, and/or all the other things we’ve learned to manage.

A digital signal remains well-behaved when its edge rate is longer than the roundtrip time on the interconnect. That intuitively makes sense, because the signal rises so slowly it doesn’t “see” imperfections in its path. As such, 12” connections were fine as long as the edge rate was at least 4 ns. Obviously, the situation has changed dramatically now that we regularly use 20 ps edge rates on 12” connections. How do we manage the challenges GHz signals have imposed, requiring us to care about even the smallest of features? Keep the roundtrip idea in mind because we’re about to re-use it to help answer this question.

A Useful Rule-of-Thumb (RoT)

In asking others about how they determine relevant feature size, my favorite response was: “any feature smaller than 0.1 UI can be ignored.” While this sounds simple enough, we need to transform time into length to readily apply it. As PCB propagation ranges from 150 to 185 ps/inch, the average conveniently yields 6 mils/ps. So we have:

Relevant In-line Feature Length >= 0.1 UI

~= 0.1*UI*6mils/ps

= 0.6*UI mils (UI in ps)

As such, the only thing to remember is 60% of a UI. For example, for 10 Gbps signals (UI=100ps) features larger than 60 mils (=0.6*100) should be carefully managed. Note the words “in-line,” meaning a feature a signal must traverse when travelling from a Tx to an Rx and not a stub.

There are a few reasons why I like this RoT:

It’s simple to remember and easily scales with data rate
It re-uses the familiar edge_rate > feature_roundtrip, because Gbps edge rates are typically 0.2*UI minimum making 0.1*UI features of concern
It agrees with the roundtrip time of the acceptable stub rule-of-thumb, or 0.3/Gbps ([2], slide 5)

Does Simulation Agree?

To test out the RoT, I constructed a typical 5” 100 Ohm 10 Gbps channel with a modern Lt/Dk of 0.006, intentionally making it short and lower-loss to accentuate the effects of discontinuities. I then constructed models of discontinuities that varied in impedance +/- 20% (80 and 120 Ohms) – similar to the range a signal encounters at vias and connectors. I inserted one discontinuity into the channel that ranged in size from 10 to 200 mils (swept in increments of 10 mils, or 20 lengths) while holding the overall channel length constant at 5”. Moving the location of the discontinuity further from the Tx in 1” increments produced the eye height versus discontinuity length plots in Figure 1. In Figure 1, each of the four colors (red, green, blue, black) represent the four distances of the discontinuity from the Tx (1”, 2”, 3”, 4”, respectively), darker shades representing the lower-impedance 80 Ohm discontinuity, and lighter shades the 120 Ohm.

Figure 1. 10 Gbps Eye Height Degradation Versus Discontinuity Length, Placement, and Impedance (Image created in MATLAB)

Figure 1 reveals a few interesting things:

The 60 mil limit (vertical black line) suggested by the RoT represents, in most cases, the knee of the curve. While eye height degradation up to 60 mils is visible in some cases, it stays below 2%. Beyond the 0.1 UI point, eye heights can decrease by 10% per 0.1 UI.
Eye height degradation increases as we move the discontinuity further from the Tx, as can be seen by comparing its placement at 1” (red), 2” (green), 3” (blue), and 4” (black).
For this case, lower impedance 80 Ohm discontinuities (darker shades) cause more degradation than higher impedance 120 Ohm discontinuities (lighter shades).

Simulating at slower data rates revealed more linear trends, with similar 2% degradation as we approach 0.6*UI mils. Degradation up to 5% at the RoT length was seen at faster data rates (20+ Gbps), confirming the adage that things won’t get simpler as we go faster. Test the RoT yourself in your simulator of choice or download a trial copy of MATLAB’s Signal Integrity Toolbox to perform a similar analysis. Be sure to post what you find in the Comments section below.

Figure 2 plots relevant Discontinuity Length versus Data Rate suggested by the RoT, and illustrates why we’ve been caring about 30 mil features as data rates exceed 16 Gbps.

Figure 2. Relevant Feature Size Versus Data Rate RoT

How Should I Apply This?

Some will say this rule-of-thumb is not strict enough while others will say it is overly conservative, which highlights the fact that it is simply a “rule-of-thumb.” In other words, it gives you a quick way to orient yourself in time and space and know how, and to what degree, to apply your engineering skills. For example, as data rates exceeded 8 Gbps via impedance became consistently relevant in PCB design. Looking at Figure 2, note that this is the data rate where RoT via length traverses the thickness of typical PCBs, or 60 to 120 mils. Once you know which discontinuities are relevant, work to both understand their impedance and then adapt that impedance to match the impedances of the surrounding interconnects.

I often spend time working on discontinuities at or below the length suggested by the rule-of-thumb. That’s because as data rates increase, today’s borderline problem is tomorrow’s headache. So, it’s best to find a solution while time is on your side. Indeed, history shows that negotiable items at one data rate become requirements in the next ([3] page 3). Pre-working items such as tapered antipad traces ([3] page 11), the removal of serpentine length matching ([3] page 12), and compensating breakout trace impedance ([4] page 23) gave me a chance to traverse the simulate/correlate loop a couple times and find solutions before the issues became problematic.

In Conclusion

Understanding and minimizing discontinuities is increasingly important as serial links become both shorter and faster. Applying the old edge rate to roundtrip relationship to the modern era, I’ve offered a rule-of-thumb to help gauge which interconnect structures, and hence discontinuities, to care about – and to what degree. I believe you’ll find the RoT a convenient metric you can easily apply. You can also use it when jumping between PCBs and packages, changing mils to microns (RoT=15*UI um).

If you have a favorite rule-of-thumb to help decide which discontinuities are relevant in a design, be sure to share it in the Comments section below.

This article is an excerpt from Donald Telian’s new book “Signal Integrity, In Practice,” a practical handbook for Hardware, SI, FPGA, and Layout Engineers.