Today’s high-speed serial transceivers are complex systems that bring to bear the best a technology process has to offer to achieve 112 Gb/s transmission rates, and beyond. A SerDes transceiver leverages analog- and digital-signal processing to compensate for channel loss, reflections, and cross talk. For 112 Gb/s operation, most mid- to long-reach SerDes rely on ADC-based receivers [7,8], such as the one shown in Fig. 1. In an ADC-based receiver the continuous-time linear equalizer (CTLE) provides analog-signal processing, while the bulk of the signal processing is performed in the digital domain via the feed-forward equalizer (FFE) and the decision-feedback equalizer (DFE). The analog and digital-signal processing paths are co-optimized to achieve the required performance targets, such as power, area, and link reach.
The design of a high-speed serial transceiver is a monumental undertaking, requiring collaboration across a multi-disciplinary team, a multi-year development cycle, and a significant monetary investment. The multi-disciplinary nature of SerDes design requires involvement from system architects, analog designers, digital designers, layout designers, firmware engineers, signal integrity engineers, and other teams. Achieving a return on investment requires on-time delivery of a fully working and inter-operable transceiver in as few design iterations as possible – ideally one.
Designing and validating such a complex system necessitates the judicious use of models [10,12]. This paper specifically focuses on the use of models for overall system validation, including both system models that evaluate the end-to-end link performance, and models used for individual block functionality to validate a mixed-signal design. We will show that these behavioral models can be automatically generated earlier in the design cycle than with conventional modeling approaches. This enables a shift-left in the design validation effort. Section 2 introduces the different models that are used during a SerDes development cycle, which represent the different levels of representation of the SerDes system. SerDes systems are complex mixed-signal systems, thus Section 3 discusses the various mixed-signal validation challenges. We then discuss the typical behavioral model generation flows used, and then we propose an alternative methodology that allows for a left-shit for mixed-signal validation. Section 4 discusses modeling requirements to enable automatic behavioral model generation. In Section 5 an architecturally accurate behavioral CTLE model is generated, which has the required input/output correspondence and is correlated to the underlying architectural model. The corresponding simplified circuit design for the CTLE is developed in Section 6, the architectural model is refined based on available circuit simulations, and an updated and circuit accurate behavioral model is automatically re-generated. Section 7 concludes this paper.
The paper referenced here was presented at DesignCon 2022. To read the entire DesignCon 2022 paper, download the PDF.
