Cadence® Sigrity™ XcitePI™ Extraction technology takes chip layout data in GDSII or LEF/DEF formats, and generates a comprehensive SPICE model that consists of a fully distributed PDN and I/O nets and accounts for all electromagnetic coupling effects between signals, power, and ground.
The models can be used in conjunction with models of package and boards for chip/package/board power-integrity (PI) or power-aware signal-integrity (SI) analysis.