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Spirent Communications has announced a collaboration with Cadence Design Systems, Inc. to deliver a joint networking system-on-chip verification solution that bridges the gap between pre-silicon and post-silicon verification.
Cadence Design Systems, Inc. and Rambus Inc. have announced that they have entered into a definitive agreement for Cadence to acquire the Rambus SerDes and memory interface PHY IP business.
The Cadence® Verisium™ Artificial Intelligence (AI)-Driven Verification Platform, a suite of applications leveraging big data and AI to optimize verification workloads, boost coverage, and accelerate root cause analysis of bugs.
Cadence Design Systems, Inc., expanded its system analysis product line with the introduction of the Cadence® Clarity™ 3D Transient Solver, a system-level simulation solution that solves electromagnetic interference (EMI) system design issues up to 10X faster than legacy 3D field solvers and offers unbounded capacity.
Cadence Design Systems, Inc. expanded its presence in the system analysis and design market with the introduction of the Cadence Celsius Thermal Solver, the first complete electrical-thermal co-simulation solution for the full hierarchy of electronic systems from ICs to physical enclosures.
Cadence® Sigrity™ XcitePI™ Extraction technology takes chip layout data in GDSII or LEF/DEF formats, and generates a comprehensive SPICE model that consists of a fully distributed PDN and I/O nets and accounts for all electromagnetic coupling effects between signals, power, and ground.
Cadence® Sigrity™ Broadband SPICE™ technology accurately and quickly converts N-port passive-network parameters such as scattering, impedance, or admittance (S, Z, or Y) into SPICE-equivalent circuits that can be used in time-domain simulations.
To keep up with the rapid advances in high-speed interfaces, you need to be able to run accurate, full-bus simulations in hours, instead of days. By converting models from transistor to power-aware IBIS behavioral, Cadence® Sigrity™ Transistor-to-Behavioral Model Conversion (T2B™) can help you meet ever-shorter deadlines by avoiding time-consuming transistor-level simulation and inaccurate non-power-aware IBIS model simulation.
The Cadence® Sigrity™ XtractIM™ tool provides a complete model extraction environment focused specifically on IC package applications. The tool generates electrical models of IC packages in IBIS or SPICE circuit netlist format. These concise parasitic models can be per pin/net RLC list, coupled matrices, or Pi/T SPICE sub-circuits.
Cadence® Sigrity™ XcitePI™ Extraction technology takes chip layout data in GDSII or LEF/DEF formats, and generates a comprehensive SPICE model that consists of a fully distributed PDN and I/O nets and accounts for all electromagnetic coupling effects between signals, power, and ground. 
Cadence® Sigrity™ Broadband SPICE™ technology accurately and quickly converts N-port passive-network parameters such as scattering, impedance, or admittance (S, Z, or Y) into SPICE-equivalent circuits that can be used in time-domain simulations.
To keep up with the rapid advances in high-speed interfaces, you need to be able to run accurate, full-bus simulations in hours, instead of days. By converting models from transistor to power-aware IBIS behavioral, Cadence® Sigrity™ Transistor-to-Behavioral Model Conversion (T2B™) can help you meet ever-shorter deadlines by avoiding time-consuming transistor-level simulation and inaccurate non-power-aware IBIS model simulation.
The Cadence® Sigrity™ XtractIM™ tool provides a complete model extraction environment focused specifically on IC package applications. The tool generates electrical models of IC packages in IBIS or SPICE circuit netlist format. These concise parasitic models can be per pin/net RLC list, coupled matrices, or Pi/T SPICE sub-circuits.