Phase-locked loops (PLL) are used extensively throughout modern electronic systems. In data communication systems, PLLs are used in transmitter clock multipliers and receiver clock recovery circuits.  A key performance factor for the PLL is how they manage jitter.  A critical PLL metric is the jitter transfer function which is based on the PLL loop bandwidth. There are several measurement methods that can be used to characterize PLL loop bandwidth and jitter transfer. When operating on digital data signals, PLL bandwidth can vary with the data pattern. Test methods that allow operation on data rather than only clock signals provide very high precision and useful insights into PLL behavior will be the focus of this article.

The phase-locked loop (PLL), as its name implies, is a form of synchronization circuit. In its most simple form, a tunable voltage-controlled oscillator is compared in frequency/phase to an incoming signal. Differences in frequency/phase result in an error voltage proportional to that difference. This voltage is then used to adjust or tune the frequency/phase of the tunable oscillator to minimize the phase difference. The tunable oscillator becomes locked or synchronized to the incoming signal. A very common application for the PLL is to derive a clock signal from a digital data signal. When in a locked state, the tunable oscillator can provide a clock signal to a decision circuit used in a system receiver.

Figure 1. Phase-locked loop block diagram.

By placing dividers or multipliers in the feedback loop between the oscillator and the phase detector, the functionality of the PLL can be extended. For example, a 2.5 GHz clock signal can be derived from a 100 MHz reference clock. The tunable oscillator, nominally around 2.5 GHz, is fed back to the phase detector through a divide by 25 circuit and compared to the 100 MHz input signal. When locked, the 2.5 GHz oscillator will be synchronized to the 100 MHz reference clock. A 100 MHz signal, more easily routed to several locations in a system than a very high rate signal, can be the reference clock used to generate higher rate clocks for several transmitters. For example, several 2.5 GHz transmitters can be created, and all will be synchronous to each other, as all are derived, using PLLs, from the same 100 MHz reference.

An important characteristic of the PLL is how the system behaves as the rate of the incoming signal varies. All real digital communications signals will have some variation in their rate whether they are clock signals or data. Variation in rate is commonly referred to as jitter and can be due to a variety of sources including phase noise, inter-symbol interference, or switching power supply interference. This is generally managed by the PLL. If the incoming signal rate changes, the error voltage from the phase detector will change. This drives the PLL oscillator which will adjust its frequency to match the incoming signal. Jitter is dynamic and causes a signal rate to vary above and below the nominal rate. How far the signal rate changes and how fast the signal rate changes are important considerations in the design of the PLL. The transfer function between the phase detector output, and the amount the PLL oscillator changes frequency, can have adjustable gain. The transfer function gain is also frequency dependent. When the feedback loop is open, the gain can be very high at low frequencies and diminishes at high frequencies. When the feedback loop is closed, the transfer function behaves like a low pass filter with unity gain at low and mid frequencies and rolling off at high frequencies. How does this effect the performance of the PLL?

If jitter is occurring at low frequencies the PLL has sufficient gain to easily track and follow the changing rate of the incoming signal. If the jitter is occurring at a very fast rate, the closed loop gain will not be sufficient to track the incoming data. A useful method to quantify this effect is to compare the jitter on the PLL output clock to the jitter on the signal coming into the PLL. Output jitter versus input jitter can be plotted versus the jitter frequency and is known as the PLL jitter transfer function (JTF). Many communications standards rely on the PLLs in receivers to be able to track jitter up to a specific frequency. Knowing the PLL jitter transfer function helps ensure adequate performance within a system. In systems like PCI-Express, endpoint devices and add-in cards have PLLs in the transmitters that use a 100 MHz reference clock to generate the full bit-rate clock used for driving the data stream at 2.5, 5, 8, 16, and 32 Gbit/s rates. A poorly designed PLL could have a jitter transfer function that exceeds unity gain over some frequency range and then amplifies jitter in that range. The transmitter PLL circuit jitter transfer bandwidth and peaking behavior must be constrained and are tested to manage jitter and ensure system interoperability. 

Characterization of PLL jitter transfer is based on a stimulus-response measurement system. The input to the PLL is a signal that has sinusoidal jitter intentionally imposed on it. The frequency of the jitter is swept over a range of interest, perhaps 200 kHz to 20 MHz. The PLL output clock is then measured to observe the magnitude of jitter that is transferred to it. The output versus input jitter is then plotted versus jitter frequency.  

Figure 2. Jitter transfer response including PLL loop bandwidth.

In digital data communication, there are several classes of devices that require this type of measurement and to measure all of them requires a flexible test system:

• Clock multiplier circuits: The input and output signals both being clocks, but the two clock rates are different
• Clock recovery circuits: The input signal is digital data and the output is a clock signal
• Repeater circuits: The input and output signals are both data, with the output being retimed with a regenerated clock
• Reference clock-based transmitters: One input is a low frequency clock, the output is high frequency data

The key features of a measurement system capable of testing all four types of devices above are an accurate method to measure jitter, both at the output of the device under test (DUT), but also the ability to measure and set the appropriate level of jitter on the input signal, over an appropriate range of jitter frequencies. Spectrum analyzers are useful tools to quantify jitter on clock signals but do not perform well on data signals due to their complex frequency spectrum.  It is difficult for the spectrum analyzer to assess peaking in the jitter transfer function at an accuracy better than 0.1 dB, required by some digital systems. Oscilloscopes are useful to quantify jitter on both clock and data signals.  Quantifying low frequency jitter can be difficult due to the long time records required.  Another approach, relatively uncommon, but growing in usage for testing PLLs for data communication, is based on a system that employs a hardware jitter demodulation system that directly extracts the jitter of a signal, whether it is a clock or data waveform.

Hardware Jitter Demodulation Performed Using a Clock Recovery System Utilizing a Scheme Similar to the Classic PLL

As discussed above, when a signal comes into the clock recovery system, an error voltage is generated at the output of the phase detector that is proportional to the difference in frequency or phase versus the local oscillator. In a very simple view, if the local oscillator is at a specific frequency, and the incoming signal varies in frequency due to jitter, the phase detector error voltage will be proportional to the jitter. In reality the system is dynamic and the local oscillator will be continually adjusted to try to match the incoming signal frequency even as the incoming frequency is changing due to jitter. Through appropriate calibrations, the error voltage output of the phase detector can be used to provide a direct measurement of the incoming jitter. This can be true for both data signals and clock signals. This achieves the most complicated element of the PLL stimulus-response test system: an accurate method to quantify jitter on both clock and data signals.

Figure 3. Instrumentation CDR block diagram for jitter demodulation.

The other required element for the PLL test system is a jitter stimulus. This is available in many forms and is dependent on the type of device being analyzed. In all cases, the stimulus needs to be able to sinusoidally frequency/phase modulate its output over a wide range of frequencies, perhaps a 200 KHz to 20 MHz range. For testing the clock recovery circuit or data repeater system a modulatable pattern generator is used. For the clock multiplier or reference clock-based transmitter, a modulatable clock source is required.

Figure 4. Test system and process for PLL jitter transfer analysis.

The first step in the PLL measurement is to calibrate the system. The jitter source (stimulus) is connected directly to the test system receiver (instrumentation-grade clock recovery). The jitter frequency is sequenced over the range of interest. Any frequency response rolloff of the test system JTF, as well as source nonlinearities, are now known and can be removed from the measurement result ensuring the performance of only the DUT and not the test system is observed. The DUT is then placed between the jitter source and receiver and response of the DUT is observed. The jitter transfer result is then analyzed to determine the PLL bandwidth as well as any peaking/gain.

Figure 5. Test results provide a precise analysis of both loop bandwidth and any JTF peaking.  

The system described above, based on an instrumentation grade hardware clock recovery system, may not be found in all R&D labs. A real-time oscilloscope is found in most labs and a method to characterize PLLs with this tool would be a great benefit to many engineers. An oscilloscope can also be used to extract the jitter of both clock and data signals. The incoming waveform is recorded as amplitude versus time. The waveform can then be analyzed to determine the time location at which the signal traverses some specific amplitude threshold, such as the 0 volt level for a signal that varies from -1 volt to +1 volt. For a simple clock signal, if it is jitter free (e.g. a constant frequency) the time difference between adjacent edges will be constant for all edges. If the time between edges varies, that variation can be analyzed to determine both the frequency and magnitude of the jitter on the incoming signal. Consider that to observe PLL behavior on a 32 Gbps signal, analysis of jitter at low frequencies requires a long waveform record in terms of symbols. Observing a single period of 100 KHz jitter would require 320 thousand symbols. An accurate analysis would benefit from observing several periods of jitter, as well as signal averaging to improve measurement repeatability, increasing the required overall acquisition length, resulting in a long measurement time. An alternate technique is required to efficiently perform PLL analysis with the real-time oscilloscope.

Rather than measuring jitter by observing the time interval between signal edges, the real-time oscilloscope can be configured as a form of spectrum analyzer.  The oscilloscope is placed in a digital down convert configuration. Using data processing in MATLAB, the jitter can be determined. The center frequency is set to the known data rate. Jitter appears as phase modulation tones. Since the PLL measurement uses known jitter tones, the jitter tones are easily identified and quantified. These are tracked as the jitter frequency is sequenced from the low to high range of the measurement, on both the stimulus to the DUT, and on the DUT output. The ratio of the output jitter to the input jitter yields the PLL loop bandwidth.  

As noted earlier, the spectrum of a data signal is complex. The spectral tones are predictable in terms of the data rate and pattern length. Through careful selection of the jitter test frequencies the jitter tones can be identified even in the presence of the complex data spectrum.  

The clock recovery based PLL measurement system is most useful for general purpose testing of a wide range of PLL-based circuits and systems. Both the clock recovery-based system and the real-time oscilloscope system are approved for PCI-Express PLL compliance testing. (The PLL measurements obtained from the clock recovery system and the real-time oscilloscope system show good agreement when testing the same DUT). Both methods have the important ability of being able to perform analysis on both data and clock signals, ensuring essential insights into the performance of PLL-based systems in data communication environments.