Articles Tagged with ''memory''

Burst Separation 12-19-23.jpg

Understanding Burst Separation for DDR5 System Validation

DDR5 Electrical and Timing Measurement Techniques

In the final installment of his article series "DDR5 Electrical and Timing Measurement Techniques," Randy White explores how following a standard workflow for setting up thresholds and timings to distinguish bursts in DDR5 memory interfaces can make design validation much more efficient, ultimately ensuring compliance with specifications and improving system margin by identifying and resolving any issues, especially those related to either read or write transactions.


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Optimizing Probing and Signal Access 12-7-23.jpg

How to Optimize Probing and Signal Access for DDR5 System Validation

DDR5 Electrical and Timing Measurement Techniques

Optimizing DDR5 memory system validation involves a strategic focus on probe and interposer solutions for in-system measurements. The selection of probe architecture, whether RC or RCRC, plays a key role in managing probe loading. To make the right choice, evaluating source impedance and signal characteristics, especially for bursted signaling, is essential. As DDR5 continues to evolve at higher speeds and reach its top speed phase, integrating non-ideal loading modeling within simulations and effectively de-embedding probe and interposer effects become critical components of a comprehensive testing plan.s


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