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Power conversion circuits with control loop(s) are everywhere in electronic systems. We must establish stability and performance metrics for control loops and their circuits. However, generally accepted metrics may not be good enough. Is a crossover frequency with 45 degrees of phase margin and 10 dB of gain margin enough? How can we relate phase margin to peaking in the impedance profile and transient noise requirements? This article aims to answer these and other questions.

VRMs and VRM controllers are often selected based on size, efficiency, price, or a relationship with the manufacturer. This often leads to a poor VRM selection, requiring additional engineering resources, greater time to market, as well as, higher BOM costs to correct the deficiencies. In this article, we evaluate the choices, define some useful figures of merit, and provide specific selection suggestions.

Yuiry Shelpnev argues that simulating a link in isolation from the rest of the board (localization) is probably the most important requirement to simulate interconnects predictably. Read on to understand this important concept.

This article examines the key noise processes involved in measurements of jitter and phase noise, shows how these processes impact test results for various types of test equipment, and provides insight for interpreting these results.

If we know how to design interconnects that correlate with the measurements for 28 Gbps NRZ, is it going to be a "free lunch" to move to 56 Gbps NRZ? Not so easily, as I learned recently. Read on to see how you can benefit from some analysis and validating your tools.

After last year’s EDI CON China event taking place in Shanghai, EDI CON China returned to Beijing at the Chinese National Convention Center directly across from the Olympic Park. Close to 3,000 unique attendees participated in the conference with more than 125 companies in the exhibition. Read this complete review of the event.

At the University of Colorado, Eric Bogatin and students Thomas Rutkowski and Huy Nguyen look for a way to validate IBIS models, bringing measured data from a scope into a simulation environment. This article includes an explanation of how the team compared predicted results of the IBIS model supplied by the vendor, the results from a generic model, and measured results from a randomly selected part.

Last night, at EDI CON China 2018, the conference and exhibition that brings together engineers working on high-frequency analog and high-speed digital designs, the winners were announced in the EDI CON Innovation Awards. This award program honors products that have had the greatest impact on the industry this year, providing the tools necessary to bring on the next generation of electronic design innovations.

A common design technique for power distribution networks (PDN) is the determination of the peak distribution bus impedance that will assure that the voltage excursions on the power rail will be maintained within allowable limits, generally referred to as the target impedance. In theory, the allowable target impedance is determined by dividing the tolerable voltage excursion by the maximum change in load current.

We are usually not worried about having via stubs on power and ground planes and shapes. Does it mean they are completely harmless?  When it comes to potential damage to high-speed signals, power-via stubs can be almost equally as bad as signal-via stubs.  Here is how and why.