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Understanding Burst Separation for DDR5 System Validation

DDR5 Electrical and Timing Measurement Techniques

In the final installment of his article series "DDR5 Electrical and Timing Measurement Techniques," Randy White explores how following a standard workflow for setting up thresholds and timings to distinguish bursts in DDR5 memory interfaces can make design validation much more efficient, ultimately ensuring compliance with specifications and improving system margin by identifying and resolving any issues, especially those related to either read or write transactions.


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Discontinuity Proximity Effect

Signal Integrity, In Practice

In this article, Donald Telian explains why discontinuities do not sum the same way as loss. Telian outlines that a failing an RL mask might indicate that Tx or Rx are simply too close to a discontinuity, causing the discontinuity proximity effect. Read on to learn more about how to to distance SerDes from discontinuities.


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