Signal Integrity

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Since woven glass PCB substrates are anisotropic, EDA design and modeling software hoping to advance AI and ML algorithms should have provisions to model anisotropic material, especially via transitions. In this article, Bert Simonovich discusses the importance of having an awareness of the test method used by CCL suppliers for accurate modeling and simulation. Simonovich covers how the use of out-of-plane Dk_z values instead of in-plane Dk_xy values for via modeling can cause misleading simulation results, which may result in reduced margins and potential compliance test failures when the design is built and tested. 

Foxconn Interconnect Technology showcased the demonstration of its 224 Gbps signal transmission through their OSFP 2x1 SMT connector Upper Port with a 1M Passive DAC at the DesignCon 2024 exhibition.

With the availability of both single-ended and differential oscilloscope probes, the question often arises as to which is best for probing low-speed differential serial data signals and why. The answer depends on trade-offs involving many factors. This article provides insight into factors to consider when choosing which type of probe is best for a given situation.  

The expansion of the resin systems in laminates has been a source of reliability problems as the electronics industry has placed ever higher demands on those used in printed circuit boards. Suppliers of these resin systems have improved their resin systems to eliminate or minimize failures from expansion as the systems using the PCBs have been made more complex and subjected to ever harsher environments. Currently, the only technologies that still suffer failures from resin expansion with temperature are triple-high stacked blind vias, which Lee Ritchey explores in this article.

Omnitron Systems has announced the launch of a new ultra-compact PoE Injector called the OmniConverter GPoE+/I.

Phase-locked loops (PLL) are used extensively throughout modern electronic systems. In data communication systems, PLLs are used in transmitter clock multipliers and receiver clock recovery circuits. A key performance factor for the PLL is how they manage jitter. A critical PLL metric is the jitter transfer function which is based on the PLL loop bandwidth. There are several measurement methods that can be used to characterize PLL loop bandwidth and jitter transfer. When operating on digital data signals, PLL bandwidth can vary with the data pattern. In this article, Greg Le Cheminant, Keysight Technologies, focuses on test methods that allow operation on data rather than only clock signals provide very high precision and useful insights into PLL behavior.

With PCIe Gen7 on the horizon, expected to debut around 2025 at a staggering 128 GT/s data rate and a pad-to-pad channel loss budget shift from -32 dB at 16GHz to -36 dB at 32 GHz, this article delves into the evolving performance requirements for Gen7 connectors and details the pivotal design changes needed to meet these demands. The study delves into meticulous design refinements in both the add-in card and baseboard components, addressing challenges such as signal integrity concerns, ground-mode resonances, and the delicate balance between signal performance and mechanical reliability.

Inova Semiconductors expands its APIX3 SerDes family with more video channels for daisy-chained display architectures. The new transmitter devices enable simultaneous transmission of multiple videos, audio, Ethernet, and data in real time at up to 12 Gbit/s.

Within the PCB industry, FR-4 materials have long been accepted as “standard” materials. However, their use was not specific to the types of board being designed. For today’s high-speed, high-frequency designs, careful engineering and material selection relative to the resin systems and glass weave styles needed will ensure that a product will work as specified, as designed, and as manufactured. In addition, the finish of the copper used in the signal and power layers also needs to be controlled in order to ensure that loss goals are met.