Signal Integrity

RSS

In the GB/s regime, accurate modeling of conductor loss and phase delay is a precursor to successful high-speed serial link designs. In this paper, a practical method to model effective permittivity and phase delay, due to conductor surface roughness, is presented. By obtaining the dielectric and roughness parameters, solely from manufacturers’ data sheets, phase delay and effective permittivity can now be easily predicted. Detailed case studies and several examples test the model`s accuracy.

Tektronix, a leading worldwide provider of measurement solutions, today introduced new equivalent time automated compliance test solutions for 4-lane 100G electrical interfaces defined in the IEEE 802.3bm and 802.3bj specifications. The new capabilities along with the full set of Tektronix solutions for 100G and 400G characterization and validation will be demonstrated February 1-2 at DesignCon 2017, Booth 741.

Anritsu Co., a DesignCon 2017 Diamond Sponsor, will present testing solutions and technical sessions to aid engineers more efficiently develop next-generation chips, boards and systems used in emerging applications, including IoT/M2M and 5G, at DesignCon, beginning January 31 in Santa Clara, CA. Signal integrity solutions featuring the award-winning Signal Quality Analyzer (SQA) MP1800A BERT, as well as the VectorStar® and ShockLine™ vector network analyzers (VNAs) will be on display in the Anritsu booth (#633) throughout the show.

An efficient computational design optimization method, combining full-wave electromagnetic simulation in COMSOL Multiphysics® software with a space-mapping (SM) algorithm implemented in MATLAB® software. 

EDI CON USA 2017, an event that brings together engineers working on high-frequency analog and high-speed digital designs, will take place at the Hynes Convention Center, September 11-13 in Boston, Mass. The event management team is pleased to announce this year’s conference chairs: Thomas Cameron, CTO for the Communications Business Unit at Analog Devices Inc. will serve as the chair for the high-frequency subject areas, and Istvan Novak, senior principal engineer at Oracle, will serve as the chair for the high-speed digital areas of the conference.

As you know, "us", Signal and Power Integrity Engineers, are full of tricks, rules of thumb, and shortcuts. These tricks mostly help us understand something, save analysis time and, why not, make us look smarter than we really are!! In that vein, seldom have I encountered a quick and dirty trick as useful and underestimated as S-parameter renormalization.

Linear Technology Corp. introduces the LTC2320-16, a 16-bit 1.5Msps per channel, no latency successive approximation register (SAR) ADC with eight simultaneously sampling channels supporting a rail-to-rail input common mode range. The LTC2320-16 features a flexible analog front end that accepts fully differential, unipolar or bipolar analog input signals, as well as arbitrary input signals, and maintains an 82dB signal-to-noise ratio (SNR) and high common mode rejection ratio (CMRR) of 102dB, when sampling input signals up to the Nyquist frequency.