Gustavo Blando

Awarded the Best Paper Award at DesignCon 2024, this paper demonstrates that, for correlated data with PDN impedances in the sub-mΩ level, the impedance extracted from same-location top-bottom measurement can be significantly different from same-side adjacent via pair measurement, even if the physical separation is in the order of a mm

In recent years, the IEEE Electrical Packaging Society technical committee for electrical design, modeling, and simulation recognized the need for open-source benchmarks for the simulation tool, verification, and test and measurement solution vendors. The intention is to overcome the obstacles that developers and users of such tools and instruments often encounter and create a growing library of benchmark cases for signal and power integrity challenges. As of October 2023, there are four published benchmark cases in the repository. This article describes a proposal for a fifth benchmark.

This paper investigates via and trace coupling effects using measurements, hybrid, and full-wave solvers by de-embedding/calibration utilizing multiple test-boards.

“Over the years I’ve come to realize that, particularly in signal integrity, half-wave resonances are often the cause of ugly S-parameters. You can argue that any type of resonance would cause problems, and you would be right. However, half-wave resonances are easily formed in topologies.” This article summarizes observations from Gustavo Blando on the formation and mitigation of half-wave resonances, and includes an in-depth study on the topic in PDF format from the author.

Gustavo Blando, a Samtec signal integrity architect, recently presented “DC Block Capacitor Location (Does It Matter)?” at a Samtec geEEk and spEEk webinar. Here he presents a summary of some of his key points.

Engineers who design and model power distribution networks require accurate component level models from high frequency down to DC.  Accurate modelling of power connectors can guarantee best power transfer and minimize power-induced noise.  In this paper, which won a DesignCon 2020 Best Paper Award, the authors analyze the frequency-dependent resistance and inductance of various power connectors as well as pin patterns.

It's a fact, the older I get, the dumber I become. I came to that realization while thinking about this eternal question engineers have about placement of high speed DC blocking caps in serial link channels. A few years ago I would have been able to recite the pros and cons without hesitation, but now, after playing manager for a few years, before I answer I have to pause and think about it. Fortunately the answer comes back quickly and I can still sleep at night. I find this topic interesting for a few reasons; one, it's a very practical issue found in almost every high speed design, and second, and perhaps more importantly, it's one of those topics were intuition might lead you the wrong way.

As you know, "us", Signal and Power Integrity Engineers, are full of tricks, rules of thumb, and shortcuts. These tricks mostly help us understand something, save analysis time and, why not, make us look smarter than we really are!! In that vein, seldom have I encountered a quick and dirty trick as useful and underestimated as S-parameter renormalization.