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John McCloskey spent almost half of his career working on the JWST. Along the way, he recorded his experiences, bringing the rest of the world along on a whirlwind journey to witness the thrills, tensions, and feats of engineering that went into his success.

Ideal circuit elements are a powerful tool that enables us to explore the real world in virtual prototypes. Engineers can often gain insights and reach an optimized design faster using a virtual prototype than would be possible when building a real physical prototype.

Eric Bogatin shares four useful tools that illustrate the dynamic nature of propagating signals, promoting the understanding that is imperative to the design of high-performance products.

In this installment, Steve Sandler discusses measuring new ultra-low impedance PDNs using newly created usable test standards in the 20 µΩ range for accurate results.

In this blog, John D'Ambrosia discusses the industry's approach to Ethernet in the age of AI, from the IEEE P802.3dj project to the efforts of the Ultra Ethernet Consortium to deliver a complete cost-effective Ethernet architecture optimized and scalable for high-performance AI. Read on to understand the role of these two complementary efforts to support AI workloads and gain insight into potential industry growth.

Artificial intelligence-generated content is rewriting the rules for data center networks, driving a need for extreme throughput and density at unprecedented scales. To meet these requirements, hyperscalers need high-performance 800G network solutions as quickly as vendors can deliver them.

As circuits shrink and bit rates increase, achieving acceptable signal integrity (SI) requires experience and creativity. It calls for foresight in layout planning to keep signal paths short, which helps minimize interference between closely spaced circuits. Circuit materials must support electrical and mechanical design specifications, and components must be selected for optimum size and placement. All these factors combine to create many challenges when developing an HSD PCB.

Crosstalk in PCB and packaging interconnects is arguably one of the most complicated phenomena that may cause signal degradation. Crosstalk effects can be treated statistically as a deterministic jitter with a bounded distribution, but the distribution is usually not known. A direct analysis of a worst-case crosstalk scenario may lead to a system overdesign. Neglecting it in design may cause a system failure that is difficult to find and fix later in a design process. Distortions caused by crosstalk cannot be corrected by signal conditioning techniques at a receiver side. It is very important to understand the sources of crosstalk, how to quantify it and how to mitigate it efficiently, as Yuriy Shlepnev demonstrates in this installation of the "How Interconnects Work" series.

In this article, Yuriy Shlepnev provides an overview of Simbeor electromagnetic signal integrity software and highlights its new features.

In the final installment of this blog series, Benjamin Dannan, Heidi Barnes, and Steve Sandler continue their discussion of how to calculate the minimum CMRR with a PDN impedance measurement using a 2-port probe, demonstrating how to measure a sub-40 µΩ impedance when using an isolator that has sufficient CMRR using two different VNAs, the Bode 100 and E5061B. Achieving sub-40 µΩ impedance measurements is challenging, but completely realistic with the proper test equipment.