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Dr. Mike Peng Li has been with Intel Corporation’s Programmable Solutions Group (formerly Altera) since 2007 and currently is an Altera Fellow. He is a corporate expert and adviser, as well as CTO office principal investigator (PI), on high-speed link technology, standard, SerDes and I/O architecture, electrical and optical signaling, silicon photonics, optical FPGA, high-speed simulation/debug/test, jitter, noise, signal and power integrity. He was the Chief Technology Officer (CTO) for Wavecrest Corporation from 2000-2007. Dr. Li is a Fellow of IEEE, and an affiliated professor at the Department of Electrical Engineering, University of Washington, Seattle. He holds a Ph.D. in physics (1991), an M.S.E (1991), in electrical and computer engineering and an M.S. in physics (1987), from the University of Alabama, Huntsville. He also holds a B.S (1985) in space physics from the University of Science and Technology of China. He was a Post Dr. and then a research scientist on high-energy astrophysics at Space Sciences Laboratory, University of California, Berkeley (1991-1995). He has more than 100 publications on refereed journals and conferences and more than 20 granted patents.
What are the optimal methods to achieve 224/212 Gb/s common electrical I/O and Ethernet, the highest speed/data rate per lane electrical input/output and link systems? By way of understanding, we begin by investigating optimal pulse amplitude modulationvs. channel characteristics at 224 Gb/s.
This paper explains the theory, implementation, constraints, and cost of using CTLE, FFE, DFE, and FEC equalization schemes for serial links at and above 112 Gbps.
