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Davide Tonietto received his Laurea Degree in 1995 from University of Pavia, Italy. Currently he is the Director of SerDes Development at Huawei Canada Research Center, Ottawa. He has more than 15 years of experience in signal integrity and high speed serial interface design and development. Previously he was Senior Manager of Signal Integrity IC development at Gennum Corporation, Manager of SerDes IP development at STMicroelectronics and lead designer of high speed serial interfaces, at Broadcom and other companies.
Architectural decisions depend on the ability to adequately analyze the link. This paper presents a methodology to model and evaluate the performance of both center and edge sampling schemes.
