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Eli Zalianski is an Electrical Validation engineer developing test methodology. He is responsible for HSIO PHY interconnect testing, silicon bring-up, and characterization. Eli specialized in 100Gbps/25Gbps PAM4/NRZ Ethernet protocols, PCIe Gen4, and DDR4/LPDDR4 JEDEC compliance testing. Eli’s experience with the channel operating margin (COM) methodology and machine learning algorithms was used to produce the data for this paper. He joined Intel in 2015 and received his BSc in Electrical Engineering from the Technion – Israel Institute of Technology in 2017.
Those interested in automating signal integrity analysis using machine learning should take a look at this work, which includes an example of a 112 Gb SerDes system analysis.
