Steve Krooswyk

Steve Krooswyk is a Senior Signal Integrity Design Engineer at Samtec. His 18 years of experience includes contributions to the design, simulation, and correlation of interconnect and I/O, as well as an influential role in PCIE standards. Prior, Steve was the PCI Express technical lead for Intel Data Center Group, co-authored the book High-Speed Digital Design: Design of High-Speed Interconnects and Signaling, and received an MS in EE from U. of South Carolina.

How To Choose an Interconnect for PCIe 6.0 High-Speed Systems

January 1, 2023

Steve Krooswyk, Anthony Fellbaum, and Matt Burns

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It’s all about the data. Loads and loads of data. How do you build a system to handle it? This article looks at interconnect options for the new PCI Express 6.0 specification: which interconnect system to choose, how to maintain signal integrity, and how to address design challenges.

PCI Express: Is 85 Ohms Really Needed?

January 5, 2021

Steve Krooswyk

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We want to follow this mantra of 85 ohms for PCIe, but it may not be so easy. Here’s a look at exactly what the spec says, and what we can do about it.

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