Abhijit Wander

Abhijit Wander, with a B.Tech in Electronics and Communication Engineering from Jaypee University, India (2011), and an M.S. in Electrical Engineering from Pennsylvania State University (2014), has carved a notable path in the electrical engineering world. Starting his career at QCard Labs (2015-2017), he played a pivotal role in crafting essential test methods for the payment industry, showcasing his knack for innovation and technical prowess. His journey took a significant leap forward in 2017 when he joined Amphenol FCI as a Senior Signal Integrity Engineer. His role entails leading the design and development of innovative high-speed and high-density connectors, with latest accomplishment being the development of the PCIe Gen7 CEM connector, which achieves an impressive data rate of 128GT/s.

Senior Signal Integrity Engineer at Amphenol FCI

Navigating Signal Integrity Challenges: Transitioning from PCIe Gen6 to Gen7

April 1, 2024

Abhijit Wander

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In the second part of this article series on navigating signal integrity challenges, Abhijit Wander showcases a marked improvement in signal integrity performance, specifically in connector-only scenarios, by transitioning from a microstrip to a stripline footprint design.

Navigating Signal Integrity Challenges: Transitioning from PCIe Gen6 to Gen7

February 21, 2024

Abhijit Wander

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With PCIe Gen7 on the horizon, expected to debut around 2025 at a staggering 128 GT/s data rate and a pad-to-pad channel loss budget shift from -32 dB at 16GHz to -36 dB at 32 GHz, this article delves into the evolving performance requirements for Gen7 connectors and details the pivotal design changes needed to meet these demands. The study delves into meticulous design refinements in both the add-in card and baseboard components, addressing challenges such as signal integrity concerns, ground-mode resonances, and the delicate balance between signal performance and mechanical reliability.

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