Items Tagged with 'loss'

In the second part of this article series on navigating signal integrity challenges, Abhijit Wander showcases a marked improvement in signal integrity performance, specifically in connector-only scenarios, by transitioning from a microstrip to a stripline footprint design.

With PCIe Gen7 on the horizon, expected to debut around 2025 at a staggering 128 GT/s data rate and a pad-to-pad channel loss budget shift from -32 dB at 16GHz to -36 dB at 32 GHz, this article delves into the evolving performance requirements for Gen7 connectors and details the pivotal design changes needed to meet these demands. The study delves into meticulous design refinements in both the add-in card and baseboard components, addressing challenges such as signal integrity concerns, ground-mode resonances, and the delicate balance between signal performance and mechanical reliability.

Serial links have focused the practice of signal integrity on managing loss and discontinuities. Each system struggles with one or the other, making it imperative to determine which issue is dominant in your system and respond appropriately. This article by Donald Telian will explain how to characterize your link to help guide your thinking and your solution.

In Donald Telian’s book he reveals his steps for successful serial links, called the “7 Steps to Successful Serial Links.” In this article, he discusses his most important steps: (one) minimize discontinuities, and (two) manage loss.