Items Tagged with 'modeling'

ARTICLES

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PCB Laminate Anisotropy: The Impact on Advanced Via Modeling

Since woven glass PCB substrates are anisotropic, EDA design and modeling software hoping to advance AI and ML algorithms should have provisions to model anisotropic material, especially via transitions. In this article, Bert Simonovich discusses the importance of having an awareness of the test method used by CCL suppliers for accurate modeling and simulation. Simonovich covers how the use of out-of-plane Dkz values instead of in-plane Dkxy values for via modeling can cause misleading simulation results, which may result in reduced margins and potential compliance test failures when the design is built and tested. 


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Design for AMI: A New Integrated Workflow for Modeling 56G PAM4 SerDes Systems

In the future, the complexity of circuit implementation will increase dramatically and modeling of high-speed SerDes systems will continue to be a huge challenge. Modeling equalization circuit characteristics has become extremely important to ensure the success of the final platform implementation and provide a strong signal integrity design guide. This paper reviews the common challenges of converting an existing detailed architectural model to an IBIS-AMI model and some of the ways to address these challenges. It also includes an illustration of the workflow to model Intel’s 56G PAM4 SerDes.


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SIJ EXECUTIVE INTERVIEW_

Executive Q&A: Larry Williams, ANSYS

SIJ had the opportunity to engage with Larry Williams, ANSYS director of technology, to find out his thoughts on how modeling and simulation needs have changed, how the industry has responded, and what’s next. At ANSYS, Larry Williams is responsible for the strategic direction of the company’s physics simulation products.


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Via Characterization and Modeling By Z Input Impedance

In high-speed digital channel design, vias are everywhere and are becoming very crucial elements to the channel performance. Especially with the higher data rate requirements in mobile, networking, and data center applications, the effect of vias in a design is very noticeable. Design engineers have traditionally used time domain reflectometry (TDR) as a tool to characterize and optimize via designs, yet the TDR approach comes with shortcomings such as demanding shorter rise-time step signal or larger bandwidth S-parameters, and inaccurate read-out on the via impedance.

In this article, we propose a simple and effective Z-input impedance method that augments the traditional TDR method for characterizing and optimizing via designs in much faster speed systems.


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