As with any design decision, selecting a backplane design approach requires tradeoffs in price, flexibility, and performance specific to a particular network topology. This article analyzes the effect on high-speed serial-link performance for a printed circuit board (PCB) backplane versus a backplane constructed of connectorized cable assemblies, particularly in terms of IEEE and OIF compliance specifications, and notes what kinds of applications might be well suited for a cable or PCB backplane.

Should I use a cable or PCB backplane in my system design? As with most questions regarding signal integrity, the answer is: it depends. In this article, we take a close look at signal integrity implications at the component and system levels for applications that require a backplane, noting performance opportunities as well as integration tradeoffs and advantages.

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224 Gb/s Per Lane: Options and Challenges

At the BOM level, a cable backplane can be more expensive than a traditional PCB backplane. But, at the system level, it can offer significant advantages by enabling earlier software development and integration activities in the front end and lower total cost of ownership on the back end. For instance, a cabled backplane can offer the flexibility to interface blades with test equipment, software development platforms, and early engineering prototype systems, all while offering high enough performance to futureproof the production solution. Additionally, the improved channel performance, or reach, with cable assemblies as compared to PCB routes can be used in some case to increase network spans and physically reach more nodes.

Figure 1 shows physical mappings for several common network topologies. In the case of the star topology outlined in the rack/chassis in the right side of the figure, the node or blade can be the same design with the same connectors, regardless of whether it has a cable or PCB backplane. As a result, it is possible to design for a PCB backplane today and migrate to a higher-speed cable backplane later, or design for a cable backplane today to achieve extra margin. This would allow for insertion of new blades and switches in the chassis later, netting substantial design and system reuse. When used as an Agile systems integration on/off ramp and potential product life cycle extender, the upside opportunities offered with cabled backplane approaches can vastly outweigh differences in component cost.


In the case of the simple ring, mesh, and star topologies (Figure 1), using a cable backplane might allow the nodes to be populated at an increased blade or module pitch (accommodating thermal design space as component power densities increase, or potentially placed in adjacent racks or chassis). Depending on the distance from the switch, when PCB loss becomes limiting, migration to cabled backplanes can be easy. 

In more complicated network topologies with many more segment crossings, cabled backplane approaches can run into scaling issues, making PCB route approaches more attractive. Additionally, PCB-based backplanes can offer advantages for co-design with other infrastructure, such as power delivery and out-of-band low speed signals.

Backplane Performance

In terms of performance, both PCB and cable backplanes can offer excellent performance at shorter channel links, while cable backplanes enable excellent signal speeds also at longer channel links. One reason cable backplanes can do this is that the traces are not running through the PCB, so each of the differential pair can go through an individual shielded cable. This can lead to less loss and better signal integrity vs. a PCB channel.

Figure 2 shows the models for a PCB backplane topology vs. a cable backplane topology, using the same BOM (see Table 1) except for the cable and the PCB backplane. The significant difference between the two topologies is the loss per unit inch between a PCB backplane (G) and a cabled backplane (G’). In this model, at 26.56 GHz (IEEE 802.3ck 400GBASE-KR4 signaling frequency), the loss for G is designed to 1.0 dB/in., and the loss for G’ is 0.25dB/in.1 Of course, there is also no PCB backplane connector vias and break out areas in the cabled backplane model, and these can be areas of significant signal integrity degradations in the channel.2

Figure 3 shows the modeled and simulated insertion loss between the topologies, described in Figure 2, with two different length options for each type of topology. The significant change is the loss between the pink traces (PCB backplane 2 and 16 in.), with the most loss in the 16 in. PCB backplane channel still providing approximately 6 dB of insertion loss margin. But is that enough? Answering this requires performing system level channel analysis.

System Level Channel Analysis

When eight lanes are plotted, assessing system level losses against PAM4 requirements using channel operating margin (COM), things do not feel quite as safe (see Figure 4). Higher data limits, such as CEI-112G-LR-PAM43 and IEEE 802.3 400GBASE-KR4,4 lead to loss of margin at the system level, especially when designing systems for cost effectiveness.

In this model of 800 GbE ports, each lane acts as a victim while the seven other lanes act as near-end transmitting aggressors. In Figure 4, the green points are at CEI-112G-LR-PAM4 while the orange are at IEEE 802.3 400GBASE-KR4; the three plots on the left are for cable backplane (G’) while the three on the right are PCB backplanes (G).

We would expect to have less margin with the higher data rates, and that is supported in this graph. Note that 4 in. of cable backplane has very similar performance to 2 in. of PCB backplane. The cable backplane demonstrates similar COM performance across all three lengths (4, 10, and 18 in.) while the PCB backplane exceeds the ability of the SERDES to compensate for loss, reflections, and crosstalk after 8 in. of backplane route length. In addition, for the 8 and 16 in. PCB backplane, note the delta between 100G and 112G speeds with the separation in COM results becoming more pronounced. For a 16 in. backplane at 112G PAM4, this system has a negative COM, despite having significant margin with respect to the OIF-CEI-112-LR insertion loss limit line.

In the past, the 6 dB margin demonstrated in Figure 3 would be a comfortable place for the designer to stop development and analysis, confident that unaccounted for error terms would be small in comparison. For 112G and higher, that is no longer the case and channels must be assessed with true end-to-end multi-lane effects at the system level including all significant regions of interconnect. Connector systems that offer options for both board-to-board and cable-to-board interconnects can be used to navigate the design trade space and offer significant opportunities for earlier integration and longer sustainment.


REFERENCES
2. B. Simonvich, “Controlling Electromagnetic Emissions from PCB Edges in Backplanes,” Signal Integrity Journal, January 2017, Web: https://www.signalintegrityjournal.com/articles/292.
3. Optical Internetworking Forum, “Common Electrical I/O (CEI) - Electrical and Jitter Interoperability agreements for 6G+ bps, 11G+ bps, 25G+ bps, 56G+ bps and 112G+ bps I/O,” Implementation Agreement OIF-CEI-05.0, May 2022, pp. 582-597. Web: https://www.oiforum.com/wp-content/uploads/OIF-CEI-5.0.pdf.
4. The IEEE 802.3ck Taskforce, Web: https://www.ieee802.org/3/ck/index.html.