DesignCon gears up to celebrate its 30th anniversary this January with special events, an expo full of leading suppliers, and its highly regarded education
Between FedEx, UPS, and Amazon Prime, it’s not unusual to find a package on my doorstep. But it’s rare that I am as delighted as I was when recently opening a package from long-time DesignCon attendee, speaker, and Technical Program Committee (TPC) member Istvan Novak.
Istvan, a globally recognized engineer with Samtec, is known for giving back more engineering knowledge than can be measured across his decades of experience. In the package, he had shared a copy of the original DesignCon event handbook, full of technical papers and speaker information from the first show held in 1995.
This year at DesignCon, as part of our 30th Anniversary celebration, we will display that very same handbook that started it all. Taking place January 28-30, 2025, at the Santa Clara Convention Center, DesignCon will host a 30th Anniversary lounge on the expo floor with a QR code to download and save the handbook. Serving as a time capsule of the history of the event, with designs and papers that laid the groundwork for today’s innovations, the handbook holds many contributions of people like Istvan, who have continued to share their insights with the design community over the past three decades.
Our 30th Anniversary celebration also includes a special Welcome Reception to mark the milestone, giveaway prizes, and a timeline wall located in the lounge space that will highlight some of the most important events and technologies over the past 30 years. There will also be a space on the timeline to predict the next big innovations, where we welcome guests to imagine what is to come for design manufacturing.
As DesignCon has for many years, the event will host a stellar education program vetted by our 99-member TPC, daily networking opportunities, and more than 170 exhibitors.
Education Highlights
While DesignCon 2024 attendee interest in optimizing high-speed link design remained strong, education in power integrity in power distribution networks, power supplies, and power delivery boasted the highest attendance. DesignCon’s TPC advises that the impressive interest in power integrity stems from the increase in the power usage of new semiconductor devices and the booming of data centers, HPC, and AI/ML processors. This increased usage brings new effects in a PDN that negatively impact the product’s performance and cause failures. Solving these problems requires new methods, new tools, and new approaches to develop PDNs for modern semiconductor devices.
Areas that showed the highest number of paper submissions for the 2025 conference (a good indicator of research activity and overall interest) were the core topics of modeling, analysis, and the optimization of interconnects and high-speed link design.
The following is a sample of the sessions rated highest by our TPC peer reviewers, with papers written and presented exclusively at DesignCon 2025:
“Balancing Current Density to High-Power ASICs in Lateral Power Delivery Designs” from Hewlett Packard engineers covers new via construction and optimization strategies.
“Statistical Modeling of System Power Integrity in Adaptive Embedded SoC for Artificial Intelligent (AI) Computing” comes from AMD engineers and examines efficient ways of modelling current consumption to help design for the increasing complexities of PDN and reducing over-design.
“Next Generation 224 Gbps-PAM4 Chip-to-Chip/MR SERDES, Package, Channels & Link Simulation & Analysis” from Intel engineers provides a thorough study on 224G analysis with an eye toward understanding design sensitivities and optimizing link operating characteristics.
“200-Gbps Lanes Equalization Methods & Required Fixture Bandwidth, S-parameter Bandwidth & Acquired Signal Bandwidth” comes from Tektronix engineers and covers the important topic of MLSD becoming a part of the link equalization.
“Via Design for 112 Gbps & Beyond: Theory & Reality” is a combined effort of Simberian and Intel engineers on how to deal with real-life problems such as manufacturing variations and tolerances, as well as the importance of EM field localization to close the gap between simulation and reality measurements.
Additional Education of Interest
- “Prediction of Dielectric Constant & Copper Roughness Parameters of High-Speed Automotive PCB Digital Interconnects Using a Data-Based Model” from the University of New Brunswick Fredericton and Institut für Theoretische Elektrotechnik
- “Tutorial – Power Delivery Network Master Class on 2000A: How to Design, Simulate & Validate“ from Keysight, Broadcom, Signal Edge Solutions, and Picotest engineers
- “Reduced Order Geometric Macro Model of PCB Fiberglass Spatial Variation for Skew & Impedance Prediction” from Samtec engineers
- “Obtaining Accurate Signal Measurements: Active Probing” from Northrop Grumman engineers
- “Panel – The Expanded Role of SI/PI in Next Gen AI Data Center Development” moderated by Tektronix.
Further Information
In total, DesignCon 2025 is offering more than 160 educational sessions. Conference passholders will have access to the 14 tracks of education, plus the Drive World automotive-focused conference. All attendees have access to keynotes, panels, Chiphead Theater presentations, exhibitor-led education, the Engineer of the Year and Best Paper Awards presentations, and the DesignCon expo floor.
With 170+ exhibitors, DesignCon’s expo floor will present some of the industry’s most influential companies, including host sponsor Amphenol, Cadence, Keysight, Molex, Mouser, Samtec, and TE Connectivity, with experts on-site to answer design questions, provide advice on engineering, and present educational demonstrations on the latest in high-speed design tools, technologies, and developments.
DesignCon’s 2025 exhibition is open Wednesday and Thursday, January 29 and 30, and the conference is presented Tuesday, Wednesday, and Thursday, January 28-30.
We’ll see you at DesignCon’s 30th Anniversary, an event as it has been for three decades: created by engineers, for engineers.
