Signal Integrity

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In this blog, John D'Ambrosia discusses the industry's approach to Ethernet in the age of AI, from the IEEE P802.3dj project to the efforts of the Ultra Ethernet Consortium to deliver a complete cost-effective Ethernet architecture optimized and scalable for high-performance AI. Read on to understand the role of these two complementary efforts to support AI workloads and gain insight into potential industry growth.

This achievement successfully verifies the ultra-low non-linear Kerr effect and ultra-low SRS effect of the hollow-core fiber system, marking a key milestone towards achieving longer-distance and larger-capacity transport over hollow-core fiber in the future.

In this field guide, David Banas of Keysight explores COM from specification to practice. From mapping out the pitfalls to avoid to explaining the discrepancies between the specification and the MATLAB code, Banas guides the link designers through a successful first experience with COM.

Samtec has announced availability of its NovaRay cable assemblies that combine extreme density and performance by using 40% less space than traditional arrays to support 112 Gbps PAM4 per channel.

This article covers the importance of proper calibration, measurement, and de-embedding to ensure that the final capacitor model is free of errors, allowing an accurate representation of the PDN used in simulation. While capacitor models may play a seemingly minor role in the overall system design, the impact of capacitor models can significantly impact the system design and, importantly, design sign-off.

The CopprLink Cable specifications provide signaling at 32.0 and 64.0 GT/s and leverage well-established industry standard connector form factors maintained by SNIA. 

Available freely to Samtec customers under NDA, SIBORG works with Ansys HFSS 3D Layout to generate, visualize, optimize, and develop PCB package and component break out regions.

Artificial intelligence-generated content is rewriting the rules for data center networks, driving a need for extreme throughput and density at unprecedented scales. To meet these requirements, hyperscalers need high-performance 800G network solutions as quickly as vendors can deliver them.

In recent years, the IEEE Electrical Packaging Society technical committee for electrical design, modeling, and simulation recognized the need for open-source benchmarks for the simulation tool, verification, and test and measurement solution vendors. The intention is to overcome the obstacles that developers and users of such tools and instruments often encounter and create a growing library of benchmark cases for signal and power integrity challenges. As of October 2023, there are four published benchmark cases in the repository. This article describes a proposal for a fifth benchmark.

In the second part of this article series on navigating signal integrity challenges, Abhijit Wander showcases a marked improvement in signal integrity performance, specifically in connector-only scenarios, by transitioning from a microstrip to a stripline footprint design.