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In this article, John Baprawski reviews various issues when using S-parameter files to represent the channel in a SerDes system channel simulator. Stepping through several detailed examples, he demonstrates how paying close attention to the quality of the S-parameters allows you to have confidence in the derived SerDes design eye diagrams and other analysis methods. 

In this overview of the principles of high-performance PCB layout, Joe Aguilar illustrates thermal design approaches, supplies a synopsis of the power delivery network (PDN), tells strategies for routing high currents with reduced impedance, and provides important considerations for designing effective decoupling capacitance. 

In this article, Donald Telian shares an excerpt from his new book, “Signal Integrity, In Practice,” exploring how optimizing SES both fixes problems and improves system performance. He posits it’s crucial for hardware and SI engineers to understand how to optimize SES; read on to see why he attributes such importance to it. 

Fiber weave effect skew, also known as glass weave skew, is becoming more of an issue as bit rates continue to soar upwards. Today’s 56 GB/s is state of the art in high-speed routers and 112 GB/s is just around the corner. Next-generation PCIe, used in the personal computer and server industry, is rapidly moving to 64 GT/s. 

In this article, Bert Simonovich shows how using Dkeff calculated from phase or time delay measurement method will lead to inaccurate simulation results for printed circuit board (PCB) transmission lines.

A high percentage of EMI failures are related to structure resonances in a system. This hands-on article reviews work on structure resonances and their EMI impact, presents methods to identify and locate structure resonances, and suggests fixes using practical examples. 

What are the optimal methods to achieve 224/212 Gb/s common electrical I/O and Ethernet, the highest speed/data rate per lane electrical input/output and link systems? By way of understanding, we begin by investigating optimal pulse amplitude modulationvs. channel characteristics at 224 Gb/s.

Understanding and minimizing discontinuities is increasingly important as serial links become both shorter and faster. Applying the old edge rate to roundtrip relationship to the modern era, Donald Telian in this article offers a rule-of-thumb to help gauge which interconnect structures, and hence discontinuities, to care about – and to what degree.  

In earlier DDR systems, the clock, command, and address signals (here in referred to as C/A) were distributed to multiple DRAMs using a forked topology, in which these signals propagate to all the DRAMs in the system at approximately the same time. The propagation delays on the command and address lines (in such systems) introduced timing skew into the system, limiting the operating frequency of the bus and eventually impacting the performance of these memory systems.

DesignCon, the premier high-speed communications and system design conference returns to its home at the Santa Clara Convention Center in Santa Clara, Calif., with technical paper sessions, tutorials, industry panels, product demos, and exhibits April 5-7, 2022.