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This article covers the importance of proper calibration, measurement, and de-embedding to ensure that the final capacitor model is free of errors, allowing an accurate representation of the PDN used in simulation. While capacitor models may play a seemingly minor role in the overall system design, the impact of capacitor models can significantly impact the system design and, importantly, design sign-off.

This article identifies the primary culprit behind the elevated radiation emission levels during CISPR-25 compliance assessments and presents practical solutions for regulatory adherence that impact automotive design and testing while supporting the evolution of more refined EMC standards. Read on to learn how this approach enhances vehicle safety and performance by addressing electromagnetic interference.

In recent years, the IEEE Electrical Packaging Society technical committee for electrical design, modeling, and simulation recognized the need for open-source benchmarks for the simulation tool, verification, and test and measurement solution vendors. The intention is to overcome the obstacles that developers and users of such tools and instruments often encounter and create a growing library of benchmark cases for signal and power integrity challenges. As of October 2023, there are four published benchmark cases in the repository. This article describes a proposal for a fifth benchmark.

In the second part of this article series on navigating signal integrity challenges, Abhijit Wander showcases a marked improvement in signal integrity performance, specifically in connector-only scenarios, by transitioning from a microstrip to a stripline footprint design.

Since woven glass PCB substrates are anisotropic, EDA design and modeling software hoping to advance AI and ML algorithms should have provisions to model anisotropic material, especially via transitions. In this article, Bert Simonovich discusses the importance of having an awareness of the test method used by CCL suppliers for accurate modeling and simulation. Simonovich covers how the use of out-of-plane Dk_z values instead of in-plane Dk_xy values for via modeling can cause misleading simulation results, which may result in reduced margins and potential compliance test failures when the design is built and tested. 

With the availability of both single-ended and differential oscilloscope probes, the question often arises as to which is best for probing low-speed differential serial data signals and why. The answer depends on trade-offs involving many factors. This article provides insight into factors to consider when choosing which type of probe is best for a given situation.  

The expansion of the resin systems in laminates has been a source of reliability problems as the electronics industry has placed ever higher demands on those used in printed circuit boards. Suppliers of these resin systems have improved their resin systems to eliminate or minimize failures from expansion as the systems using the PCBs have been made more complex and subjected to ever harsher environments. Currently, the only technologies that still suffer failures from resin expansion with temperature are triple-high stacked blind vias, which Lee Ritchey explores in this article.

Phase-locked loops (PLL) are used extensively throughout modern electronic systems. In data communication systems, PLLs are used in transmitter clock multipliers and receiver clock recovery circuits. A key performance factor for the PLL is how they manage jitter. A critical PLL metric is the jitter transfer function which is based on the PLL loop bandwidth. There are several measurement methods that can be used to characterize PLL loop bandwidth and jitter transfer. When operating on digital data signals, PLL bandwidth can vary with the data pattern. In this article, Greg Le Cheminant, Keysight Technologies, focuses on test methods that allow operation on data rather than only clock signals provide very high precision and useful insights into PLL behavior.

With PCIe Gen7 on the horizon, expected to debut around 2025 at a staggering 128 GT/s data rate and a pad-to-pad channel loss budget shift from -32 dB at 16GHz to -36 dB at 32 GHz, this article delves into the evolving performance requirements for Gen7 connectors and details the pivotal design changes needed to meet these demands. The study delves into meticulous design refinements in both the add-in card and baseboard components, addressing challenges such as signal integrity concerns, ground-mode resonances, and the delicate balance between signal performance and mechanical reliability.

Within the PCB industry, FR-4 materials have long been accepted as “standard” materials. However, their use was not specific to the types of board being designed. For today’s high-speed, high-frequency designs, careful engineering and material selection relative to the resin systems and glass weave styles needed will ensure that a product will work as specified, as designed, and as manufactured. In addition, the finish of the copper used in the signal and power layers also needs to be controlled in order to ensure that loss goals are met.