Dan Lin

Feng (Dan) Lin received the Ph.D. degree in Electrical Engineering (EE) from the University of Idaho, Boise, ID in 2000, and M.S. and B.S. degrees in EE from the University of Electrical Science and Technology of China in 1995 and 1992 respectively. He joined DRAM Design R&D at Micron Technology, Inc., Boise in 2000, focusing on the development of high-speed, leading edge DRAM for high-performance computing. He most recently serves as the lead designer in Signal Integrity R&D team for advanced memory architecture and future I/O development. Dr. Lin is a co-author of the textbook DRAM Circuit Design, Fundamental and High-Speed Topics (Wiley-IEEE Press, 2008). Dr. Lin holds over 117 U.S. and foreign patents to date.

16Gb/s and Beyond with Single-Ended I/O in High-Performance Graphics Memory

January 1, 2019

Tim Hollis, Salman Jiva, Martin Brox, Wolfgang Spirkl, Thomas Hein, Dave Ovard, Roy Greeff, Dan Lin, Michael Richter, Peter Mayer, Walt Moden, Maksim Kuzmenka, Mani Balakrishnan, Milena Ivanov, Manfred Plan, Marcos Alvarez Gonzalez, Bryce Gardiner, Dong Soon Lim, and Jörg Weller

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The paper discusses the development of GDDR6 as a lower-risk and more cost-effective solution as compared to other high-bandwidth memory solutions.

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