Items Tagged with 'impedance'

In this article, Steve Sandler presents several methods of measuring battery impedance, discussing the reasons for conducting such measurements and the challenges one might encounter along the way.

In this installment, Steve Sandler discusses measuring new ultra-low impedance PDNs using newly created usable test standards in the 20 µΩ range for accurate results.

In the second part of this article series on navigating signal integrity challenges, Abhijit Wander showcases a marked improvement in signal integrity performance, specifically in connector-only scenarios, by transitioning from a microstrip to a stripline footprint design.

With PCIe Gen7 on the horizon, expected to debut around 2025 at a staggering 128 GT/s data rate and a pad-to-pad channel loss budget shift from -32 dB at 16GHz to -36 dB at 32 GHz, this article delves into the evolving performance requirements for Gen7 connectors and details the pivotal design changes needed to meet these demands. The study delves into meticulous design refinements in both the add-in card and baseboard components, addressing challenges such as signal integrity concerns, ground-mode resonances, and the delicate balance between signal performance and mechanical reliability.

In the final installment of this blog series, Benjamin Dannan, Heidi Barnes, and Steve Sandler continue their discussion of how to calculate the minimum CMRR with a PDN impedance measurement using a 2-port probe, demonstrating how to measure a sub-40 µΩ impedance when using an isolator that has sufficient CMRR using two different VNAs, the Bode 100 and E5061B. Achieving sub-40 µΩ impedance measurements is challenging, but completely realistic with the proper test equipment. 

As voltage margins for power rails continue to decrease, end-to-end power integrity modeling is already difficult without having to be concerned if all of your simulation models are correct. System designers typically assume that all of the vendor models are correct. So, what does an engineer do if one of the ASIC die models needed for a power integrity simulation is incorrect? 

In the process of circuit design, electrical engineers must carefully position capacitors to decouple the power supply pins of integrated circuits (ICs). Yet, relying solely on a single capacitor for this purpose may potentially decrease the performance of the Power Delivery Network (PDN). Therefore, there exists a need for an elegant and systematic methodology in designing the PDN while utilizing a single capacitor. Within this paper, we analyze the single-capacitor scenario within the context of the PDN and introduce a systematic approach for its design. This approach not only suggests clear guidelines for when favoring a single capacitor over multiple capacitors is appropriate but also showcases that when these guidelines are exceeded, this method can be implemented recursively to achieve an optimal PDN solution.

This paper investigates via and trace coupling effects using measurements, hybrid, and full-wave solvers by de-embedding/calibration utilizing multiple test-boards.

Reduction of microstrip FEXT plays an important role in microwave engineering, as microstrip coupled line backward couplers suffer from poor directivity when not compensated. In this article, Henning Mextorf presents a general approach to improve directivity which does not require a modification of the dimensions of the coupled line structure and provides closed form solutions for optimum capacitor values.

Successfully designing a PCB with more than one impedance while maintaining a manufacturable and economical product can be a difficult challenge. By examining the histories and uses of various impedances, Lee Ritchey simplifies the process and discusses the ideal impedance for PCB stackup design.