Items Tagged with 'Interconnects'

Designed for testing Ethernet and IP speeds up to 100 Gbps, PacketExpert 100G is ideal for evaluating high-speed backhaul networks and data center interconnects.

Crosstalk in PCB and packaging interconnects is arguably one of the most complicated phenomena that may cause signal degradation. Crosstalk effects can be treated statistically as a deterministic jitter with a bounded distribution, but the distribution is usually not known. A direct analysis of a worst-case crosstalk scenario may lead to a system overdesign. Neglecting it in design may cause a system failure that is difficult to find and fix later in a design process. Distortions caused by crosstalk cannot be corrected by signal conditioning techniques at a receiver side. It is very important to understand the sources of crosstalk, how to quantify it and how to mitigate it efficiently, as Yuriy Shlepnev demonstrates in this installation of the "How Interconnects Work" series.

In its new report, "Co-packaged Optics for Datacenter 2023," Yole Intelligence investigates CPO technology.

It’s all about the data. Loads and loads of data. How do you build a system to handle it? This article looks at interconnect options for the new PCI Express 6.0 specification: which interconnect system to choose, how to maintain signal integrity, and how to address design challenges.

About 150 years ago the first stable transatlantic cable was laid and messages were sent between Ireland and Newfound­land over copper. The data rate on this cable was not even 1 bit/sec, it was 0.1 bit/sec. Concerns over the cable reliabil­ity and the slow data rate led some to believe copper was doomed as a communication media for these long cables.

Modeling and measurement of digital serial interconnects is usually done in the frequency domain. That means that the minimal and maximal frequencies (or bandwidth) should be defined even before the analysis or measurement begins. This post introduces a simple and practical way to identify the bandwidth with a numerical analysis of defects in a single bit (SBR) or single symbol response (SSR).

Ever wonder how much energy is required to transmit data and why so much power is dissipated into heat? SIJ EAB member Yuriy Shlepnev takes a closer look.

The first goal in any high-speed board stack up design is to engineer interconnects with a target impedance, and the first step in this process is to use a 2D field solver to explore design space with a virtual prototype. Just how well can a field solver predict the impedance of traces on a real board? This article aims to answer this question.

What is special about a material like PTFE that gives it such a low Dk and Df, while an epoxy has such a high Dk and Df? It is all about the chemical structure of the molecules and how they interact. Understanding the connection between chemistry and electrical properties is the starting place to engineer optimized materials for high-speed interconnects.

There was a time when the signal integrity of connections between digital ICs could be nearly ensured by following one simple rule: don’t connect more than some maximum number of input pins to any single output pin. Often the fanout limit would be around 7. No models, no simulations. Everything we needed was in the thick books of vendor datasheets that filled our shelves, the tree-killing viral precursor to AOL installation CDs. Ah, those were the days!