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This DesignCon 2022 paper presents a parametric ADC-based SerDes system modeling framework intended to support all project phases from architectural definition, through analog and digital design, to design validation.
In Donald Telian’s book he reveals his steps for successful serial links, called the “7 Steps to Successful Serial Links.” In this article, he discusses his most important steps: (one) minimize discontinuities, and (two) manage loss.
If you’ve just started on the path of designing high-speed serial links or have designed dozens of your own, Don Telian’s Signal Integrity in Practice is the book that will accelerate your engineering judgment and possibly save you from multiple design spins. Eric Bogatin takes a closer look at what he considers a must-have book for new and experienced engineers.
Recent studies indicate that the industry is nearing the precipice where plated through hole via technology has reached a limit in supporting serial links with 28 GHz Nyquist frequency requirements. At DesignCon2021, a team from the Mayo Clinic presented this paper about their work to extend the “life” of conventional PCB technology.
Future data center and high-speed computation require faster connectivity to meet the increasing set of applications and bandwidth. IEEE and OIF have developed 106-112 Gbps per lane electrical interface specifications P802.3ck1 and CEI-112 G2 for the 400 GbE system. To meet the next-generation system bandwidth requirement, industry and standard bodies recently kicked off new projects aiming at 800 GbE or even higher speeds beyond 1 TbE. So what comes next beyond 112 Gbps for electrical interfaces over copper (Cu) channels? Will it be 224 Gbps?
This paper explains the theory, implementation, constraints, and cost of using CTLE, FFE, DFE, and FEC equalization schemes for serial links at and above 112 Gbps.
