Introduction

The impedance target required in today’s high-power electronic systems is  around 100 μΩ or less. The design and measurement procedures developed in the last few decades must be re-visited and updated to meet these aggressive goals. In the measurements of low-impedance systems with wafer probes on the same side of the DUT, the probe coupling creates errors in the impedance profiles. A big part of the analysis in this paper is based on VNA measurements and simulations. The VNA calibration procedures are crucial and will be carefully described (see full text). 

This paper investigates three major aspects of PDN measurements:

  1. The spatial effects associated with large via arrays in low-impedance PDNs
  2. The impact of via coupling within the Device Under Test 
  3. The impact of probe-tip coupling in wafer probe calibrations and measurements

The purpose of this paper is to explore these relationships and provide guidance to correctly take the spatial and other 3D effects into account. 

The figure above visualizes the three areas of investigation with a 3D rendering of two single-ended wafer probes touching down on the corner of a large via array, illustrating the three main areas of investigation: 

  1. spatial effects,
  2. via-loop coupling, and
  3. probe-tip coupling. 

Two boards are used in this work. The first one is a test board developed for the IEEE Electrical Packaging Society (EPS) technical committee on electrical design, modeling, and simulation. The second board used for this investigation is a production board for high-power ASICs for ML/AI workloads, referred to as the “Production board” below. The impedance target is approximately 45 μΩ

Several aspects of the simulation setup impact the quality of the results: the choice of solver, extraction settings, boundary conditions, and frequency sweep among others. For this study, a full wave 3D FEM solver has been used almost exclusively . 

Measurement Setup and Calibration

This paper focuses on low-impedance PDN structures. In frequency-domain impedance measurements these conditions call for a two-port shunt-through connection scheme with provision to suppress the cable-braid loop error. The frequency range was 100 Hz to 10 MHz logarithmic sweep with 10 Hz or lower IFBW.

Measurement to Simulation Correlation

J84 structure was examined on the IEEE Board (Section 6), as it provides the shortest as well as longest via launch. (See the full paper for details.)

Figure 1 Novak 10-18024.pngJ84 close-up on IEEE board (left), and 3D view with only pads, vias and layer 2 visible. All vias connect to layer 2 (right).

The figure below shows results from both measurements and simulation. Straight probe configuration is shown in blue, flipped in red and average of the two in yellow, and simulation results in green. To summarize, as expected, two-port probing on opposite sides gives best predictability in the measurements, while for same side probing, measurement limits the effective bandwidth over which we can expect results to correlate.

Figure 2 Novak 10-18-24.png

The IEEE Board Section 2 was used to analyze distributed plane effects. Starting with individual ports at some set points in the design, these ports are placed both on the side that a device might be mounted as well as on the reverse side (mimicking measuring the PDN on the rear of the card). 

Figure 3 Novak 10-18-24.png

The resistance and loop inductance for both simulated and measured cases were compared for three positions: upper left-hand side, middle, and middle right-hand side on the top (component side) surface.  

The results are presented in the full paper in Figure 5, showing reasonable correlation of the PDN inductance to the measurement. Figure 6 shows the correlation between simulations and measurement data of the Production Board. Comparing this inductance range to the top measurements, one can see that the coupling inductance ranges from 20 pH to 30 pH, potentially masking our PDN inductance. The next step is to use the correlated simulation environment to help us understand how the excitation point impacts the PDN impedance by parameterize port grouping:   

  1. Grouping ¼ of the pins (Blue)
  2. Grouping ½ of the pins (Red)
  3. Grouping ¾ of the pins (Purple)
  4. Grouping all pins (Green)

Figure 7 shows that by grouping more balls, the impedance minima and inductance decreases significantly, as expected. The inductance and impedance minima follow hyperbolically decreasing values as the number of VDD and VSS balls is increased.

Conclusion

This paper demonstrates that, for correlated data with PDN impedances in the sub-mΩ level, the impedance extracted from same-location top-bottom measurement can be significantly different from same-side adjacent via pair measurement even if the physical separation is in the order of a mm. It was also shown that grouping many pins in an array yields simulated impedance similar to what one can obtain from top-bottom VNA measurement in the center of the via field.

The paper referenced here received the Best Paper Award at DesignCon 2024. To read the entire DesignCon 2024 paper, download the PDF.