Items Tagged with 'DesignCon 2024'

ARTICLES

DesignCon Paper Summary Samtec 10-18-24.jpg

Impact of Finite Interconnect Impedance Including Spatial and Domain Comparison of PDN Characterization

DesignCon 2024 Best Paper Award Winner

Awarded the Best Paper Award at DesignCon 2024, this paper demonstrates that, for correlated data with PDN impedances in the sub-mΩ level, the impedance extracted from same-location top-bottom measurement can be significantly different from same-side adjacent via pair measurement, even if the physical separation is in the order of a mm



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Samtec DesignCon Paper Summary Cover.jpg

Are 1.0 mm Precision RF Connectors Required for 224 Gbps PAM4 Verification?

DesignCon 2024 Best Paper Award Winner

This paper, awarded the Best Paper Award at DesignCon 2024, explores what is meant by bandwidth during the standardization process, the implications of test and verification attached to certain bandwidth requirements, as well as differences between acquisition range, band limited filters, and s-parameters for time domain processing. 


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200+ Gbps Ethernet Forward Error Correction (FEC) Analysis Cover 9-3-24.jpg

200+ Gbps Ethernet Forward Error Correction (FEC) Analysis

DesignCon 2024 Best Paper Award Winner

In order to study what is needed and what has been adopted for the next Ethernet speed node of 200 Gbps per lane, this DesignCon 2024 paper, a recipient of the Best Paper Award, investigates different FEC schemes such as end-end, concatenated, and segmented FECs, examining how these different FEC schemes affect signal integrity and performance in different end applications. 


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