Items Tagged with 'DesignCon Paper'

Awarded the Best Paper Award at DesignCon 2024, this paper demonstrates that, for correlated data with PDN impedances in the sub-mΩ level, the impedance extracted from same-location top-bottom measurement can be significantly different from same-side adjacent via pair measurement, even if the physical separation is in the order of a mm

This paper, awarded the Best Paper Award at DesignCon 2024, explores what is meant by bandwidth during the standardization process, the implications of test and verification attached to certain bandwidth requirements, as well as differences between acquisition range, band limited filters, and s-parameters for time domain processing. 

In order to study what is needed and what has been adopted for the next Ethernet speed node of 200 Gbps per lane, this DesignCon 2024 paper, a recipient of the Best Paper Award, investigates different FEC schemes such as end-end, concatenated, and segmented FECs, examining how these different FEC schemes affect signal integrity and performance in different end applications. 

This DesignCon 2024 paper, a Best Paper Award winner, introduces a new process utilizing heuristics to determine laminate anisotropy based on Dk/Df construction tables provided by laminate suppliers.

This DesignCon paper showcases high-speed design and testing schemes for LPO systems from a system perspective while also presenting the testing results, data, and product architecture of a linear direct-drive switch in conjunction with an LPO module system.

This paper comprehensively addresses the numerous challenges presented when designing a power distribution network for a scalable 2000 Amp power supply and provides a complete process for designing, simulating, and validating a 2000 Amp core power rail. 

This paper addresses the challenge of how to simulate the power integrity ecosystem and include the feedback loop and switching noise of a switch mode power supply (SMPS) without waiting days for the simulation results. The solution presented here uses control loop theory state space equations to create a behavioral model of an SMPS that allows for fast simulation.

This paper investigates via and trace coupling effects using measurements, hybrid, and full-wave solvers by de-embedding/calibration utilizing multiple test-boards.

The roughness of copper foils has a detrimental effect on signal loss in PCBs. Therefore, reducing roughness is crucial in minimizing signal loss. Nevertheless, roughness is essential to ensure a good adherence between the prepreg and the copper foil. A compromise must be found between adherence and power integrity. This paper presents a novel approach to evaluate signal loss without assuming any specific roughness shape.    

This paper demonstrates a step-by-step correlation methodology adapted for DSP-based PCIe Gen5 and Gen6 IBIS-AMI models where one can measure and directly correlate raw errors out of the DSP on a test setup that is based on the receiver stress eye methodology of the PCIe standard.