Articles Tagged with ''PCB''

Engineers invest tens to hundreds of thousands of dollars in signal integrity simulation software—the goal being to gain an accurate understanding of how signals are going to behave in the final product. But how do you do that early in the design process without reliable, verifiable electrical properties for the dielectrics incorporated into your design?

When starting a new project, board designers are often overwhelmed when trying to choose appropriate diff pair geometry, board material, and stackup to meet high-speed serial link loss budgets. Part of the printed circuit board (PCB) interconnect challenge is modeling transmission lines accurately. 

Why does a low cost through-hole SMA have a lower bandwidth than a surface mount SMA? The answer will surprise you.

This paper is a case study on causality problems in PDNs during power-aware SI simulations. It covers the causality of a PDN, and it reveals the impact on a design if a causality check is not done on the PDN for the package or board.

If performance matters, if the interconnects are not transparent, or if you want to develop good habits, you will want to incorporate these seven habits in your next two layer board design.

In high-speed circuit designs, power integrity (PI) and electromagnetic interference (EMI) are connected together. When the edge of the cavity created by power (PWR) and ground (GND) planes in PCBs radiates, the peak frequencies in the emissions are the same as the peak frequencies in the cavity self-impedance.

The power electronics engineer and the power integrity engineer share a common goal: provide the system with the correct voltages, currents, and noise characteristics to achieve the desired performance. Unfortunately, they do not share much else. They generally use different tools, vocabulary, and figures of merit. As a result, both sides lose.

Yuiry Shelpnev argues that simulating a link in isolation from the rest of the board (localization) is probably the most important requirement to simulate interconnects predictably. Read on to understand this important concept.

If we know how to design interconnects that correlate with the measurements for 28 Gbps NRZ, is it going to be a "free lunch" to move to 56 Gbps NRZ? Not so easily, as I learned recently. Read on to see how you can benefit from some analysis and validating your tools.