Articles Tagged with ''PAM4''

The continued progression to higher data rates puts increasing demands on the design of practical SerDes channels. At 112G-PAM4, the UI is only 17.86 ps, and signal transmission in the PCB must be highly optimized for loss, reflections, crosstalk, and power integrity. This article summarizes the key elements of a study that describes the signal-integrity and power-integrity design process and shows simulated SI and PI performance correlated to measured data as well as measured eye diagrams of a test board that uses a 112G-capable silicon and high-speed compression-mount cable connectors. 

With the growth of 5G data traffic and AI computing, data centers need faster connectivity to meet the increasing bandwidth. High speed I/O speed beyond 112 Gb/s per lane is required. If we follow the SerDes technology revolution by doubling the data rate per lane in every 2-3 years, the next generation I/O data rate will be 224 Gb/s. In this article, Cathy Liu explores options, technical challenges, and potential solutions to achieve 224 Gb/s per lane.

In the future, the complexity of circuit implementation will increase dramatically and modeling of high-speed SerDes systems will continue to be a huge challenge. Modeling equalization circuit characteristics has become extremely important to ensure the success of the final platform implementation and provide a strong signal integrity design guide. This paper reviews the common challenges of converting an existing detailed architectural model to an IBIS-AMI model and some of the ways to address these challenges. It also includes an illustration of the workflow to model Intel’s 56G PAM4 SerDes.

Convergence in technology is not a new idea. The concept infers that disparate technologies evolve to a closer association or integration over time. Convergence occurs when any number of technologies, such as micro twinax cables, ASIC design, interconnects, advanced IC packaging, and others combine to offer a unique system-level solution. Many see convergence as required for 224 Gbps PAM4 system performance. 

What are the test challenges brought on by PAM4? This article details what a BERT needs to do to meet the necessary signal analysis requirements.

Routing 112 Gbps PAM4 signals through a system poses many challenges for designers. In this piece, SI expert Scott McMorrow explains what causes signal degradation and offers a path forward.

SIJ gets Dr. McMillan’s take on what matters for noise generation in SI/PI design, and how PAM4 is arriving.

Interested in performance analysis for 100+ Gb/s per lane PAM4 interfaces? This paper takes a detailed look at high-speed serial link error propagation models and different Ethernet coding schemes as part of FEC performance analysis for 100/200/400 GbE systems with 100+ Gb/s per lane PAM4 interfaces.

This paper explains the theory, implementation, constraints, and cost of using CTLE, FFE,  DFE, and FEC equalization schemes for serial links at and above 112 Gbps.

That’s the question that will trigger your amygdala’s fight or flight response as you encounter the many annoyances that PAM4 brings to your world. Since you’re in a lab rather than a jungle, that fight or flight response might translate into sarcastic cracks like: “Right, that higher BER requirement makes it all so much easier—not.” “Good old NRZ, those were some fine bits. Remind me why I asked for this?” And, “dear NRZ, I never knew how much I loved you until I lost you.”