Voice of the Experts: Signal Integrity

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In this blog, John D'Ambrosia discusses the industry's approach to Ethernet in the age of AI, from the IEEE P802.3dj project to the efforts of the Ultra Ethernet Consortium to deliver a complete cost-effective Ethernet architecture optimized and scalable for high-performance AI. Read on to understand the role of these two complementary efforts to support AI workloads and gain insight into potential industry growth.

SIJ editorial advisory board member Yuriy Shlepnev offers a comparison of three ways to visualize the same s-parameter data, identifying how to get the most information from a plot.

Bends in PCB traces look like very basic, simple structures that are easy to simulate. Technically, one can do the analysis with any electromagnetic solver with sufficiently accurate port de-embedding capabilities. The reflections from a bend in fine-line, high-speed digital interconnects are relatively small and may not even be detectable with measurement. So, who cares? Read on to find out more.

Data usage is increasing every year, and the communications industry is working diligently to support the increased demand. This article discusses why we need more data, what data center physical layer architecture changes are needed to support higher data rates, and how connector manufacturers are improving designs to support higher data rate systems.

The continued progression to higher data rates puts increasing demands on the design of practical SerDes channels. At 112G-PAM4, the UI is only 17.86 ps, and signal transmission in the PCB must be highly optimized for loss, reflections, crosstalk, and power integrity. This article summarizes the key elements of a study that describes the signal-integrity and power-integrity design process and shows simulated SI and PI performance correlated to measured data as well as measured eye diagrams of a test board that uses a 112G-capable silicon and high-speed compression-mount cable connectors. 

We want to follow this mantra of 85 ohms for PCIe, but it may not be so easy. Here’s a look at exactly what the spec says, and what we can do about it.

Gustavo Blando, a Samtec signal integrity architect, recently presented “DC Block Capacitor Location (Does It Matter)?” at a Samtec geEEk and spEEk webinar. Here he presents a summary of some of his key points.

Mechanical needs and power limits are at odds with what is optimal for signal integrity. Having a metric that guides us to the sufficient SI choice rather than going for the optimal SI choice ultimately saves cost and decreases time to market. Read on for the details on Brandon Gore’s technique.

Bert Simonovich explains why you should take your shot at becoming an industry influencer, offering tips to get started and to keep moving.

Bert Simonovich reminisces about the problems and innovations that led to the invention of the point to multipoint non-contact interconnect bus.